ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 200

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.3.4
18.3.5
8077H–AVR–12/09
INTFLAGS - RTC Interrupt Flag Register
CNT3 - Counter Register 3
• Bits 1:0 - OVFINTLVL[1:0]: RTC Overflow Interrupt Enable
These bits enable the RTC Overflow Interrupt and select the interrupt level as described in
tion 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
interrupt will trigger when the OVFIF in the INTFLAGS register is set
• Bits 7:2 - Reserved
These bits are reserved and will always be read as zero.
• Bit 1 - COMPIF: RTC Compare Match Interrupt Flag
This flag is set on the next count after a Compare Match condition occurs. The flag is cleared
automatically when RTC compare match interrupt vector is executed. The flag can also be
cleared by writing a one to its bit location.
• Bit 0 - OVFIF: RTC Overflow Interrupt Flag
This flag is set on the next count after an Overflow condition occurs. The flag is cleared automat-
ically when RTC overflow interrupt vector is executed. The flag can also be cleared by writing a
one to its bit location
CNT3, CNT2, CNT1 and CNT0 registers represent the 32-bit value CNT. CNT counts positive
clock edges on the RTC clock.
Synchronization of a new CNT value to the RTC domain is triggered by writing CNT3. The syn-
chronization time is up to 12 Peripheral clock cycles from updating the register until this has an
effect in RTC domain. Write operations to CNT register will be blocked if the SYNCBUSY flag is
set.
The Synchronization of CNT value from RTC domain to System Clock domain can be done by
writing one to the SYNCCNT bit in the CTRL register. The updated and synchronized CNT regis-
ter value is available after eight Peripheral Clock cycles.
After writing to the high byte of the CNT register, the condition for setting OVFIF and COMPIF,
as well as the Overflow and Compare Match Wakeup condition, will be disabled for the following
two RTC clock cycles.
Bit
+0x03
Read/Write
Reset Value
Bit
+0x07
Read/Write
Reset Value
R/W
7
7
-
R
0
0
6
-
R
0
R/W
6
0
5
-
R
0
R/W
5
0
4
-
R
0
R/W
4
0
CNT[31:24]
3
R
-
0
R/W
3
0
2
-
R
0
COMPIF
R/W
2
0
R/W
1
0
R/W
1
0
OVFIF
R/W
0
0
XMEGA A
R/W
0
123. The enabled
0
INTFLAGS
CNT3
Sec-
200