ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 338

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.3
8077H–AVR–12/09
TAP - Test Access Port
When using the JTAG interface for Boundary-scan, the JTAG TCK clock frequency can be
higher than the internal device frequency. The System Clock in the device is not required for
Boundary-scan.
The JTAG interface is accessed through four of the AVR's pins. In JTAG terminology, these pins
constitute the Test Access Port - TAP. These pins are:
The IEEE std. 1149.1-2001 also specifies an optional TAP signal; TRST - Test ReSeT. This is
not available.
When the JTAGEN Fuse is unprogrammed or the JTAG Disable bit is set the JTAG interface is
disabled. The four TAP pins are normal port pins and the TAP controller is in reset. When
enabled, the input TAP signals are internally pulled high and the JTAG is enabled for Boundary-
scan operations.
Figure 28-1. TAP Controller state diagram
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
machine.
(Scan Chains).
XMEGA A
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