ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 306

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Atmel AVR XMEGA AU
• Bit 5 – DREIF: Data Register Empty Flag
This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is
one when the transmit buffer is empty and zero when the transmit buffer contains data to be
transmitted that has not yet been moved into the shift register. DREIF is set after a reset to indi-
cate that the transmitter is ready. Always write this bit to zero when writing the STATUS register.
DREIF is cleared by writing DATA. When interrupt-driven data transmission is used, the data
register empty interrupt routine must either write new data to DATA in order to clear DREIF or
disable the data register empty interrupt. If not, a new interrupt will occur directly after the return
from the current interrupt.
• Bit 4 – FERR: Frame Error
The FERR flag indicates the state of the first stop bit of the next readable frame stored in the
receive buffer. The bit is set if the received character had a frame error, i.e., the first stop bit was
zero, and cleared when the stop bit of the received data is one. This bit is valid until the receive
buffer (DATA) is read. FERR is not affected by setting the number of stop bits used, as it always
uses only the first stop bit. Always write this bit location to zero when writing the STATUS
register.
This flag is not used in master SPI mode operation.
• Bit 3 – BUFOVF: Buffer Overflow
This flag indicates data loss due to a receiver buffer full condition. This flag is set if a buffer over-
flow condition is detected. A buffer overflow occurs when the receive buffer is full (two
characters) with a new character waiting in the receive shift register and a new start bit is
detected. This flag is valid until the receive buffer (DATA) is read. Always write this bit location to
zero when writing the STATUS register.
This flag is not used in master SPI mode operation.
• Bit 2 – PERR: Parity Error
If parity checking is enabled and the next character in the receive buffer has a parity error, this
flag is set. If parity check is not enabled, this flag will always be read as zero. This bit is valid until
the receive buffer (DATA) is read. Always write this bit location to zero when writing the STATUS
register. For details on parity calculation, refer to
”Parity Bit Calculation” on page
296.
This flag is not used in master SPI mode operation.
• Bit 1 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 0 – RXB8: Receive Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. When used, this bit must be read before reading the low bits from DATA.
This bit is unused in master SPI mode operation.
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