ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 370

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.16.5
28.16.6
8331A–AVR–07/11
PRESCALER – Clock Prescaler register
INTFLAGS – Interrupt Flag register
Table 28-8.
• Bit 7:3 – Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2:0 – PRESCALER[2:0]: ADC Prescaler configuration
These bits define the ADC clock relative to the Peripheral clock, according to
page
Table 28-9.
• Bit 7:4 – Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
PRESCALER[2:0]
101
110
111
370.
000
001
010
011
100
101
110
111
R
R
7
–
0
7
–
0
ADC Event Mode Select (Continued)
ADC Prescaler settings
SYNCSWEEP
SWEEP
R
6
–
0
R
6
–
0
Group Configuration
R
5
–
0
R
5
–
0
DIV128
DIV256
DIV512
DIV16
DIV32
DIV64
One sweep of all ADC channels defined by SWEEP on
incoming event channel with the lowest number, defined by
EVSEL
One sweep of all active ADC channels defined by SWEEP on
incoming event channel with the lowest number, defined by
EVSEL. The ADC is flushed and restarted for accurate timing.
Reserved
DIV4
DIV8
R
4
–
0
R
4
–
0
R
3
–
0
R/W
Atmel AVR XMEGA AU
3
0
R/W
2
0
R/W
System clock division factor
2
0
CH[3:0]IF
PRESCALER[2:0]
R/W
1
0
R/W
1
0
128
256
512
16
32
64
4
8
R/W
0
0
R/W
0
0
Table 28-9 on
PRESCALER
INTFLAGS
370