M55800A Atmel Corporation, M55800A Datasheet - Page 103

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.10
ARM DDI 0029G
Reset sequence after power up
nRESET
nMREQ
D[31:0]
nEXEC
A[31:0]
It is good practice to reset a static device immediately on power-up, to remove any
undefined conditions within the device that can otherwise combine to cause a DC path
and consequently increase current consumption. Most systems are reset by using a
simple RC circuit on the reset pin to remove the undefined states within devices whilst
clocking the device.
During reset, the signals nMREQ and SEQ show internal cycles where the address bus
continues to increment by two or four bytes. The initial address and increment values
are determined by the state of the core when nRESET was asserted. They are undefined
after power up.
After nRESET has been taken HIGH, the ARM core does two further internal cycles
before the first instruction is fetched from the reset vector (address
takes three MCLK cycles to advance this instruction through the
Fetch-Decode-Execute stages of the ARM instruction pipeline before this first
instruction is executed. This is shown in Figure 3-22.
nRESET must be held asserted for a minimum of two MCLK cycles to fully reset the
core.
You must reset the EmbeddedICE Logic and the TAP controller as well, whether the
debug features are used or are not. This is done by taking nTRST LOW for at least T
no later than nRESET.
In Figure 3-22, x, y, and z are incrementing address values.
MCLK
SEQ
Note
Copyright © 1994-2001. All rights reserved.
x
y
z
Fetch 1
0
Figure 3-22 Reset sequence
Decode 1
4
Memory Interface
Execute 1
). It then
8
3-33
bsr
,