SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 457

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.7.2
Name:
Address:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
31
23
15
–
–
–
7
DDRSDRC Refresh Timer Register
-3
)/8192) x100 x10
30
22
14
DDRSDRC_RTR
0xFFFFE804
Read-write
See
–
–
–
6
Table 30-16
29
21
13
–
–
–
5
6
= 781 or 0x030D.
28
20
12
–
–
–
4
COUNT
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
COUNT
25
17
–
–
9
1
SAM9G35
SAM9G35
470.
24
16
–
–
8
0
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