SAM9G15 Atmel Corporation, SAM9G15 Datasheet
SAM9G15
Specifications of SAM9G15
Related parts for SAM9G15
SAM9G15 Summary of contents
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... Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package • 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9G15 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 11052AS–ATARM–27-Jul-11 ...
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... Description The SAM9G15, based on the ARM926EJ-S processor, runs at 400 MHz and integrates a rich set of peripherals to support embedded industrial applications that require advanced user inter- faces and high-speed communication. The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration (pic- ture-in-picture, alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4/5-wire resistive touchscreen panels ...
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... Block Diagram Figure 2-1. SAM9G15 Block Diagram 11052AS–ATARM–27-Jul-11 PIO PIO SAM9G15 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9G15 4 gives details on the signal name classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... MCI0_DA0-MCI0_DA3 Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11052AS–ATARM–27-Jul-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMediaCard Interface - HSMCI0-1 SAM9G15 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock PWM0-PWM3 Pulse Width Modulation Output SAM9G15 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Pulse Width Modulation Controller- PWMC ...
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... Soft Modem Signal DIBP Soft Modem Signal 11052AS–ATARM–27-Jul-11 USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS LCD Controller - LCDC Analog-to-Digital Converter - ADC Soft Modem - SMD SAM9G15 Type Active Level Analog Analog Analog Analog Analog Analog ...
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... Package and Pinout The SAM9G15 is available in a 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. SAM9G15 8 shows the orientation of the 217-ball BGA Package. Orientation of the 217-ball BGA Package ...
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... EBI_CLK RSTJTAG SYSC VBG 11052AS–ATARM–27-Jul-11 SAM9G15 I/O Type Description Voltage Range Analog 1.65-3.6V 1.65-3.6V 1.65-3.6V 3.0-3.6V I 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 3.0-3.6V 1.65-3.6V 0.9-1.1V I 3.0-3.6V I/O 3.0-3.6V I/O 1.65-3.6V I/O 3.0-3.6V I/O SAM9G15 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 16mA 40mA (peak) 50 (3.3V) 133 30 (1.8V) 50 (3.3V (1.8V) 133 0.25 10 0.25 10 ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: SAM9G15 10 SAM9G15 I/O Type Assignment and Frequency (Continued) I/O Frequency Charge Load (MHz) (pF 480 10 ...
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... I/O TCLK0 I/O TCLK1 I/O TCLK2 I/O TIOB0 I/O TIOB1 I/O TIOB2 I/O TWD0 I/O TWCK0 PB0 I/O PB1 I/O PB2 I/O PB3 I/O PB4 I/O PB5 I/O PB6 I/O AD7 I PB7 I/O AD8 I SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O SPI1_NPCS1 O I SPI0_NPCS2 O O MCI1_DA1 I/O I MCI1_DA2 I/O I/O MCI1_DA3 I SPI0_NPCS1 O I SPI1_NPCS0 I I/O MCI1_DA0 I/O I/O MCI1_CDA ...
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... VDDIOP1 GPIO PC24 M2 VDDIOP1 GPIO PC25 P2 VDDIOP1 GPIO PC26 M1 VDDIOP1 GPIO PC27 K4 VDDIOP1 GPIO PC28 N1 VDDIOP1 GPIO_CLK PC29 R2 VDDIOP1 GPIO_CLK2 PC30 N2 VDDIOP1 GPIO PC31 SAM9G15 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O AD9 I I/O AD10 I I/O AD11 I I/O AD0 I I/O AD1 I I/O AD2 I I/O AD3 I I/O AD4 ...
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... D23 I/O D24 I/O D25 I/O D26 I/O D27 I/O D28 I/O D29 I/O D30 I/O D31 SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal A20 O O A23 O O A24 O O A25 ...
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... A16 B17 VDDIOM EBI_O A17 E15 VDDIOM EBI_O A18 E14 VDDIOM EBI_O A19 B9 VDDIOM EBI_O NCS0 B8 VDDIOM EBI_O NCS1 D9 VDDIOM EBI_O NRD C9 VDDIOM EBI_O NWR0 C7 VDDIOM EBI_O NWR1 SAM9G15 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O NBS0 O NBS2/DQM NWR2 ...
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... I/O I/O I BMS I I TST I TCK I TDI I TDO O TMS XIN I O SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... Power Considerations 5.1 Power Supplies The SAM9G15 has several types of power supply pins. Table 5-1. SAM9G15 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. SAM9G15 16 Powers ARM core, internal memories, internal peripherals and part of the system controller ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 11052AS–ATARM–27-Jul-11 each quarter of the page system flexibility 32-bit data interface (Words) SAM9G15 ® ® technology for Java 17 ...
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... APB/AHB Bridge The SAM9G15 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridges. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...
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... Master 0 Master 1 Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 6.5 Matrix Slaves The Bus Matrix of the SAM9G15 product manages 9 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...
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... SMD USB Device High Speed DPR 3 USB Host EHCI registers USB Host OHCI registers 4 External Bus Interface 5 DDR2 Port 1 6 DDR2 Port 2 7 DDR2 Port 3 8 Peripheral Bridge 0 9 Peripheral Bridge 1 SAM9G15 2&3 4&5 DMA 0 DMA ...
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... USB The SAM9G15 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...
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... The hardware interface numbers are also given in . Table 6-4. Instance name HSMCI0 SPI0 SPI0 USART0 USART0 USART1 USART1 TWI0 TWI0 TWI2 TWI2 UART0 UART0 SSC SSC SAM9G15 22 DMA Channel Definition DMA Channel HW T/R interface Number RX/ ...
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... Instance name HSMCI1 SPI1 SPI1 SMD SMD TWI1 TWI1 ADC DBGU DBGU UART1 UART1 USART2 USART2 11052AS–ATARM–27-Jul-11 DMA Channel Definition DMA Channel HW T/R interface Number RX/ SAM9G15 Table 23 ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register ® IEEE 1149.1 JTAG Boundary-scan on All Digital Pins. SAM9G15 24 11052AS–ATARM–27-Jul-11 ...
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... Memories Figure 7-1. SAM9G15 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3 ...
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... Embedded Memories 7.2.1 Internal SRAM The SAM9G15 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 7.2.2 Internal ROM The SAM9G15 embeds an Internal ROM, which contains the SAM-BA At any time, the ROM is mapped at address 0x0010 0000 ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported 11052AS–ATARM–27-Jul-11 Average Latency of Transactions) SAM9G15 27 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 8-1 Figure 7-1 SAM9G15 28 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller peripherals. ...
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... Figure 8-1. SAM9G15 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 PB0-PB18 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 0 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.3 Backup Section The SAM9G15 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G15. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller SYS System Controller Interrupt ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9G15 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection 11052AS–ATARM–27-Jul-11 peripherals Sensors and data per chip select SAM9G15 33 ...
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... Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo SAM9G15 34 modulation and demodulation 11052AS–ATARM–27-Jul-11 ...
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... Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 11052AS–ATARM–27-Jul-11 SAM9G15 2 S, TDM Buses, Magnetic Card Reader, ...) 35 ...
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... LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 12-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources SAM9G15 36 ™ Interface (HSMCI) 11052AS–ATARM–27-Jul-11 ...
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... DMA chaining support for multiple non-contiguous data blocks through use of linked – Scatter support for placing fields into a system memory area from a contiguous 11052AS–ATARM–27-Jul-11 enabled channels lists transfer. Writing a stream of data into non-contiguous fields in system memory SAM9G15 37 ...
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... Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface • Interrupt – Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition SAM9G15 38 11052AS–ATARM–27-Jul-11 ...
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... Type I Caller ID (CID) decoding • Sixty-three embedded and upgradable country profiles • Embedded AT commands • SmartDAA – Extension pick-up detection – Digital line protection – Line reversal detection – Line-in-use detection – Remote hang-up detection – Worldwide compliance 11052AS–ATARM–27-Jul-11 SAM9G15 39 ...
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... Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing SAM9G15 40 11052AS–ATARM–27-Jul-11 ...
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... Device and 217-ball BGA Package Maximum Weight 450 Table 11-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-3. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-4. Soldering Information Ball Land Solder Mask Opening 11052AS–ATARM–27-Jul- MO-205 e1 0.43 mm ± 0.05 0.30 mm ± 0.05 SAM9G15 41 ...
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... SAM9G15 Ordering Information Table 12-1. SAM9G15 Ordering Information Ordering Code AT91SAM9G15-CU SAM9G15 42 Package Package Type BGA217 Green Temperature Operating Range Industrial -40°C to 85°C 11052AS–ATARM–27-Jul-11 ...
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... Revision History Doc. Rev Comments 11052AS First issue 11052AS–ATARM–27-Jul-11 SAM9G15 Change Request Ref. 43 ...
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... SAM9G15 44 11052AS–ATARM–27-Jul-11 ...
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