SAM9G25 Atmel Corporation, SAM9G25 Datasheet
SAM9G25
Specifications of SAM9G25
Related parts for SAM9G25
SAM9G25 Summary of contents
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... Synchronous Output • Packages – 217-ball BGA, pitch 0.8 mm – 247-ball BGA, pitch 0.5 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9G25 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 11032AS–ATARM–27-Jul-11 ...
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... SDRAM/LPSDRAM, static memories, as well as specific circuitry for MLC/SLC NAND Flash with integrated ECC bits. The SAM9G25 is available in a 217-ball BGA package with 0.8mm ball pitch, as well as a 247- ball BGA package with 0.5mm ball pitch, making it ideally suited for space-constrained applications ...
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... Block Diagram Figure 2-1. SAM9G25 Block Diagram 11032AS–ATARM–27-Jul-11 PIO PIO SAM9G25 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9G25 4 gives details on the signal names classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11032AS–ATARM–27-Jul-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9G25 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock SAM9G25 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Image Sensor Interface - ISI Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx ...
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... ADVREF ADC Reference 11032AS–ATARM–27-Jul-11 Pulse Width Modulation Controller- PWMC USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS Ethernet 10/100 - EMAC Analog-to-Digital Converter - ADC SAM9G25 Type Active Level Output Analog Analog Analog Analog Analog ...
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... Table 3-1. Signal Description List (Continued) Signal Name Function DIBN Soft Modem Signal DIBP Soft Modem Signal SAM9G25 8 Soft Modem - SMD Type Active Level I/O I/O 11032AS–ATARM–27-Jul-11 ...
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... Package and Pinout The SAM9G25 is available in 217-ball BGA and 247-ball BGA packages. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. 4.2 Overview of the 247-ball BGA Package Figure 4-2 Figure 4-2. 11032AS–ATARM–27-Jul-11 shows the orientation of the 217-ball BGA Package. Orientation of the 217-ball BGA Package ...
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... SAM9G25 10 SAM9G25 I/O Type Description Voltage Range Analog 1.65-3.6V 1.65-3.6V 1.65-3.6V 3.0-3.6V I 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- Reset State 3.6V 1.65-1.95V, 3.0- 3.6V 3.0-3.6V Reset State 1.65-3.6V Reset State 0.9-1.1V I 3.0-3.6V I/O 3.0-3.6V I/O 1.65-3.6V I/O 3.0-3.6V I/O SAM9G25 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 16mA 40mA (peak) 50 (3.3V) 133 30 (1.8V) 50 (3.3V (1.8V) 133 0.25 10 0.25 10 Pull-up ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: 11032AS–ATARM–27-Jul-11 SAM9G25 I/O Type Assignment and Frequency (Continued) I/O Frequency Charge Load (MHz) (pF ...
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... PB0 D4 VDDANA GPIO PB1 D2 VDDANA GPIO PB2 E4 VDDANA GPIO PB3 D1 VDDANA GPIO_CLK PB4 E3 VDDANA GPIO PB5 B3 VDDANA GPIO_ANA PB6 C2 VDDANA GPIO_ANA PB7 SAM9G25 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O TXD0 I/O RXD0 I/O RTS0 I/O CTS0 I/O SCK0 I/O TXD1 I/O RXD1 I/O TXD2 I/O RXD2 I/O DRXD ...
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... AD4 I ERXCK I/O AD5 I ECRS I/O AD6 I ECOL I/O IRQ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O FIQ SAM9G25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O O PCK1 O O PCK0 O O PWM0 O O PWM1 O I PWM2 O I PWM3 ADTRG I ISI_D0 I TWD1 ISI_D1 I TWCK1 ISI_D2 I TIOA3 ISI_D3 I TIOB3 ...
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... GND GNDANA R12 VDDPLLA POWER VDDPLLA T13 VDDOSC POWER VDDOSC U13 GNDOSC GND GNDOSC H14, K8, VDDCORE POWER VDDCORE K9 H8, J8, GNDCORE GND GNDCORE K10 SAM9G25 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O NANDOE I/O NANDWE I/O A21/NANDALE I/O A22/NANDCLE I/O NCS3 I/O NWAIT I/O D16 I/O D17 I/O D18 ...
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... A14 O A15 O A16 O BA0 O A17 O BA1 O A18 O BA2 O A19 SDCS NWRE O SAM9G25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... RSTJTAG RTCK P10 VDDIOP0 RSTJTAG NRST T11 VDDIOP0 RSTJTAG NTRST A6 VDDBU CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT SAM9G25 16 Primary Alternate PIO Peripheral A Dir Signal Dir Signal O NBS1 O O NBS3/DQM3 I/O I/O I ...
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... PA31 I/O TWCK0 PB0 I/O ERX0 PB1 I/O ERX1 PB2 I/O ERXER PB3 I/O ERXDV PB4 I/O ETXCK PB5 I/O EMDIO PB6 I/O AD7 I EMDC PB7 I/O AD8 I ETXEN SAM9G25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O SPI1_NPCS1 O I SPI0_NPCS2 O O MCI1_DA1 I/O ETX0 I MCI1_DA2 I/O ETX1 I/O MCI1_DA3 I/O ETXER SPI0_NPCS1 O I ...
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... PC23 M6 VDDIOP1 GPIO PC24 L3 VDDIOP1 GPIO PC25 M8 VDDIOP1 GPIO PC26 M2 VDDIOP1 GPIO PC27 L5 VDDIOP1 GPIO PC28 N3 VDDIOP1 GPIO_CLK PC29 M5 VDDIOP1 GPIO_CLK2 PC30 SAM9G25 18 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O AD9 I ETXER I/O AD10 I ETX0 I/O AD11 I ETX1 I/O ETX2 I/O ETX3 I/O ERX2 I/O ERX3 ...
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... D27 PD18 I/O D28 PD19 I/O D29 PD20 I/O D30 PD21 I/O D31 SAM9G25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal I PCK1 A20 O O A23 O O A24 ...
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... GNDCORE V19 VDDUTMII POWER VDDUTMII W18 VDDUTMIC POWER VDDUTMIC V18 GNDUTMI GND GNDUTMI F14 VDDIOM EBI E15 VDDIOM EBI C16 VDDIOM EBI D15 VDDIOM EBI SAM9G25 20 Primary Alternate PIO Peripheral A Dir Signal Dir Signal ...
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... BA2 O A19 SDCS O NRD O O NWRE O O NBS1 O NBS3/DQM SAM9G25 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... VDDIOP0 RSTJTAG NRST P9 VDDIOP0 RSTJTAG NTRST C7 VDDBU CLOCK XIN32 B7 VDDBU CLOCK XOUT32 V13 VDDOSC CLOCK XIN V12 VDDOSC CLOCK XOUT B8 Not Connected V14 Not Connected SAM9G25 22 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O I I/O DFSDP I/O I/O DFSDM I/O I/O DHSDP ...
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... Power Considerations 5.1 Power Supplies The SAM9G25 has several types of power supply pins. Table 5-1. SAM9G25 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. 11032AS–ATARM–27-Jul-11 ...
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... Separate Masters for both instruction and data access providing complete Matrix – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit SAM9G25 24 each quarter of the page ...
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... APB/AHB Bridge The AT91SAM9G25 product embeds two separated APB/AHB bridges. This architecture enables to make concurrent access on both bridges. Each peripheral can be clocked at a lower speed (MCK divided clock) in order to decrease the current consumption. 6.3 Bus Matrix • 12-layer Matrix, handling requests from 11 masters • ...
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... Master 1 Master 2&3 Master 4&5 Master 6 Master 7 Master 8 Master 9 Master 10 6.5 Matrix Slaves The Bus Matrix of the AT91SAM9G25 product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 6-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 ...
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... All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 1. AT91SAM9G25 Master to Slave Access Masters 0 ...
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... USB The AT91SAM9G25 features the following USB communication ports: • 2 Hosts (A and B) High Speed (EHCI) and Full Speed (OHCI) • 1 Host (C) Full Speed only (OHCI) • 1 Device High Speed The High Speed USB Host Port A is shared with the High Speed USB Device port and con- nected to the second UTMI transceiver ...
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... SPI0 SPI0 USART0 USART0 USART1 USART1 TWI0 TWI0 TWI2 TWI2 UART0 UART0 SSC SSC 11032AS–ATARM–27-Jul-11 DMA Channel Definition DMA Channel HW T/R interface Number RX/ SAM9G25 Table 29 ...
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... The hardware interface numbers are also given in Table 6-4. Instance name HSMCI1 SPI1 SPI1 SMD SMD TWI1 TWI1 ADC DBGU DBGU UART1 UART1 USART2 USART2 USART3 USART3 SAM9G25 30 DMA Channel Definition DMA Channel HW T/R interface Number RX/ ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. 11032AS–ATARM–27-Jul-11 SAM9G25 31 ...
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... Memories Figure 7-1. SAM9G25 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 EBI 256 MBytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 256 MBytes DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI 256 MBytes ...
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... Embedded Memories 7.2.1 Internal SRAM The SAM9G25 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 7.2.2 Internal ROM The SAM9G25 embeds an Internal ROM, which contains the SAM-BA program ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported SAM9G25 34 Average Latency of Transactions) 11032AS–ATARM–27-Jul-11 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 8-1 Figure 7-1 11032AS–ATARM–27-Jul-11 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller peripherals. SAM9G25 35 ...
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... Figure 8-1. SAM9G25 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC 12M RC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 3 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 8.2 Backup Section The SAM9G25 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... SAM9G25 38 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G25. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller System Controller Interrupt SYS PIOA,PIOB Parallel I/O Controller A and B ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9G25 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions ...
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... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection SAM9G25 40 peripherals Sensors and data per chip select ...
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... Two UARTs • Independent receiver and transmitter with a common programmable Baud Rate Generator • Even, Odd, Mark or Space Parity Generation • Parity, Framing and Overrun Error Detection • Automatic Echo, Local Loopback and Remote Loopback Channel Modes 11032AS–ATARM–27-Jul-11 SAM9G25 41 ...
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... Compatibility with MMC Plus Specification Version 4.3 • Compatibility with MultiMedia Card Specification Version 4.1 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE ATA SAM9G25 TDM Buses, Magnetic Card Reader, ...) 11032AS–ATARM–27-Jul-11 ...
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... External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Compare level interrupt for background signal surveillance 11032AS–ATARM–27-Jul-11 enabled channels SAM9G25 43 ...
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... DMAC1 is optimized for peripheral-to-memory transfers, without PIP support • Acting as Two Matrix Masters • Embeds 8 unidirectional channels with programmable priority • Address Generation – Source / destination address programming – Address increment, decrement or no change SAM9G25 44 11032AS–ATARM–27-Jul-11 ...
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... Writing a stream of data into non-contiguous fields in system memory transfer programmed values at the end of a block transfer of block transfer in block chaining mode to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition SAM9G25 45 ...
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... Type I Caller ID (CID) decoding • Sixty-three embedded and upgradable country profiles • Embedded AT commands • SmartDAA – Extension pick-up detection – Digital line protection – Line reversal detection – Line-in-use detection – Remote hang-up detection – Worldwide compliance SAM9G25 46 11032AS–ATARM–27-Jul-11 ...
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... Mechanical Overview Figure 11-1. 217-ball BGA Package Drawing 11032AS–ATARM–27-Jul-11 SAM9G25 47 ...
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... Table 11-1. 217-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-2. Package Reference JEDEC Drawing Reference JESD97 Classification Table 11-3. Soldering Information Ball Land Solder Mask Opening SAM9G25 48 3 MO-205 e1 0.43 mm ± 0.05 0.30 mm ± 0.05 11032AS–ATARM–27-Jul-11 ...
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... Figure 11-2. 247-ball BGA Package Drawing 11032AS–ATARM–27-Jul-11 SAM9G25 49 ...
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... Soldering Information Ball Land Solder Mask Opening Table 11-6. Device and 247-ball BGA Package Maximum Weight 177 Table 11-7. 247-ball BGA Package Characteristics Moisture Sensitivity Level Table 11-8. Package Reference JEDEC Drawing Reference JESD97 Classification SAM9G25 50 0.5 mm +/- 0.05 0.3 mm +/- 0.05 0.35 mm +/- 0.05 0.27 mm +/- 0. none e1 11032AS–ATARM–27-Jul-11 ...
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... SAM9G25 Ordering Information Table 12-1. SAM9G25 Ordering Information Ordering Code AT91SAM9G25-CU AT91SAM9G25-CFU 11032AS–ATARM–27-Jul-11 Package Package Type BGA217 Green BGA247 Green SAM9G25 Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C 51 ...
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... SAM9G25 52 11032AS–ATARM–27-Jul-11 ...
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