SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 44

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

10.11 Ethernet 10/100 MAC (EMAC)
10.12 Image Sensor Interface (ISI)
10.13 8-channel DMA (DMAC)
44
SAM9G25
• supports MII Mode
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operations
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
• Support Wake On Lan: The receiver supports Wake on LAN by detecting the following events
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• programmable Frame capture rate
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
• Preview scaler to generate smaller size image
• DMA on preview and codec paths
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
on incoming receive frames:
FIFO on channel 0
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match
– Source / destination address programming
– Address increment, decrement or no change
11032AS–ATARM–27-Jul-11