SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 101

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.3
ARM DDI0198D
Enabling the caches
On reset, the ICache and DCache entries are all invalidated and the caches are disabled.
The caches are not accessed for reads or writes. The caches are enabled using the I, C,
and M bits from CP15 c1, and can be enabled independently of one another. Table 4-1
gives the I and M bit settings for the ICache, and the associated behavior. The priority
of the TCM and cache behavior is described in TCM and cache access priorities on
page 4-8.
Table 4-2 gives the page table C bit settings for the ICache (CP15 c1 I bit = M bit = 1).
CP15
c1 I bit
0
1
1
Page
table
C bit
0
1
Copyright © 2001-2003 ARM Limited. All rights reserved.
Description
Noncachable
Cachable
CP15
c1 M bit
-
0
1
ARM926EJ-S behavior
ICache disabled. All instruction fetches are fetched from external
memory (AHB).
ICache enabled, MMU disabled. All instruction fetches are
cachable, with no protection checks. All addresses are flat mapped,
that is VA = MVA= PA.
ICache enabled, MMU enabled. Instruction fetches are cachable or
noncachable depending on the page descriptor C bit (see Table 4-2),
and protection checks are performed. All addresses are remapped
from VA to PA, depending on the page entry, that is the VA is
translated to an MVA, and the MVA is remapped to a PA.
ARM926EJ-S behavior
memory.
Cache hit
Cache miss
ICache disabled. All instruction fetches are fetched from external
Table 4-1 CP15 c1 I and M bit settings for the ICache
Table 4-2 Page table C bit settings for the ICache
Read from the ICache.
Linefill from external memory.
Caches and Write Buffer
4-5