SAM3S8C Atmel Corporation, SAM3S8C Datasheet - Page 396

• Manufacturer Part Number: SAM3S8C
• Manufacturer: Atmel Corporation

Figure 23-18. TDF Period in NCS Controlled Read Operation (TDF = 3)
23.11.2
396
396
SAM3S8/SD8
SAM3S8/SD8
TDF Optimization Enabled (TDF_MODE = 1)
A[23:0]
D[7:0]
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the
SMC takes advantage of the setup period of the next access to optimize the number of wait
states cycle to insert.
Figure 23-19
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
MCK
NRD
NCS
shows a read access controlled by NRD, followed by a write access controlled by
tpacc
NCS controlled read operation
TDF = 3 clock cycles
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12