AD9266 Analog Devices, AD9266 Datasheet - Page 29

• Manufacturer Part Number: AD9266
• Description: 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9266

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Addr
(Hex)
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
0x2A
AD9266-Specific Customer SPI Control Register
0x10
1
Register Name
Output mode
Output adjust
Output phase
Output delay
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
OR/MODE select
USR2
Bit 7
(MSB)
DCO output
polarity
0 = normal
1 = inverted
Enable DCO
delay
B7
B15
B7
B15
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
00 = 3.3 V CMOS
10 = 1.8 V CMOS
drive strength
3.3 V DCO
Bit 6
Open
B6
B14
B6
B14
Open
Bit 5
Open
Enable
data
delay
B5
B13
B5
B13
00 = 1 stripe
01 = 2 stripes
11 = 4 stripes
10 = 3 stripes (default)
drive strength
1.8 V DCO
Open
Bit 4
Output
disable
B4
B12
B4
B12
BIST signature, Bits[7:0]
Open
Rev. 0 | Page 29 of 32
Open
Bit 3
Open
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
B3
B11
B3
B11
Enable
GCLK
detect
drive strength
3.3 V data
Bit 2
Output
invert
B2
B10
B2
B10
Run
GCLK
(Value is number of input clock
cycles of phase delay)
Input clock phase adjust, Bits[2:0]
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Bit 1
00 = offset binary
01 = twos complement
10 = gray code
11 = offset binary
1.8 V data drive strength
B1
B9
B1
B9
Open
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
Bit 0
(LSB)
B0
B8
B0
B8
0 = MODE
1 = OR
(default)
Disable
SDIO pull-
down
Default
Value
(Hex)
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x08
Comments
Configures the
outputs and the
format of the data.
Determines CMOS
output drive
strength properties.
On devices that use
global clock divide,
determines which
phase of the divider
output is used to
supply the output
clock; internal
latching is
unaffected.
Sets the fine
output delay of the
output clock but
does not change
internal timing.
User-defined
pattern, 1 LSB.
User-defined
pattern, 2 LSB.
Least significant
byte of BIST
signature, read only.
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or
OR (output) on
External Pin 23.
Enables internal
oscillator for clock
rates of <5 MHz.
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 MSB.
AD9266