AD9266 Analog Devices, AD9266 Datasheet - Page 7

• Manufacturer Part Number: AD9266
• Description: 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9266

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
Standby
D15_D14
D1_D0
CLK+
CLK–
DCO
V
IN
2
N – 1
1
A
)
SKEW
CH
)
)
PD
DCO
)
)
N
J
)
t
t
D15
D1
CLK
t
CLK
A
DCO
N–9
t
t
N–9
)
PD
SKEW
D14
D0
N + 1
N–9
N–9
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
D15
D1
N–8
N–8
D14
D0
N + 2
Min
50/25
3
N–8
t
N–8
SKEW
AD9266-20/AD9266-40
Figure 2. CMOS Output Data Timing
D15
D1
N–7
N–7
Typ
25.0/12.5
1.0
0.1
3
3
0.1
9
350
600/400
2
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N + 3
D14
D0
N–7
N–7
D15
D1
N–6
N–6
N + 5
D14
D0
Max
80/320
20/40
N–6
N–6
D15
D1
N–5
N–5
Min
3
15.38
N + 6
D14
D0
N–5
N–5
AD9266-65
D15
D1
N–4
Typ
7.69
1.0
0.1
3
3
0.1
9
350
300
2
N–4
N + 7
D14
D0
N–4
N–4
Max
520
65
N + 8
Min
3
12.5
AD9266-80
Typ
6.25
1.0
0.1
3
3
0.1
9
350
260
2
Max
625
80
AD9266
Unit
MHz
MSPS
ns
ns
ns
ps rms
ns
ns
ns
Cycles
μs
ns
Cycles