AD6659 Analog Devices, AD6659 Datasheet - Page 30

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
HARDWARE INTERFACE
The pins described in Table 14 constitute the physical interface
between the programming device of the user and the serial port
of the AD6659. When using the SPI interface, SCLK and CSB
function as inputs. SDIO is bidirectional, functioning as an input
during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD6659 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SDIO/DCS and SCLK/DFS serve a dual function when the SPI
interface is not being used. When the pins are strapped to DRVDD
or ground during device power-on, they are associated with a
specific function. The Digital Outputs section describes the
strappable functions supported on the AD6659.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
SDIO/DCS, SCLK/DFS, OEB, and PDWN serve as standalone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the duty cycle stabilizer, output data format,
output enable, and power-down feature control. In this mode,
connect the CSB pin to DRVDD, which disables the serial port
interface.
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Table 15. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD6659 part-specific features are described in
detail in Table 17.
Table 16. Features Accessible Using the SPI
Feature
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
External Voltage
DRVDD
AGND (default)
DRVDD
AGND (default)
DRVDD
AGND (default)
DRVDD
AGND (default)
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter
offset
Allows the user to set test modes to place
known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or standby
Normal operation