AD6659 Analog Devices, AD6659 Datasheet - Page 36

• Manufacturer Part Number: AD6659
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Specifications of AD6659

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD6659
QEC Initial Gain 0 and QEC Initial Gain 1 (Register 0x116
and Register 0x117)
Bits[14:0]—Initial Gain[14:0]
When the force gain bit (Register 0x111, Bit 0) is set high, these
values are used for gain error correction.
QEC Initial Phase 0 and QEC Initial Phase 1 (Register 0x118
and Register 0x119)
Bits[12:0]—Initial Phase[12:0]
When the force phase bit (Register 0x111, Bit 1) is set high,
these values are used for phase error correction.
QEC Initial DC I (Register 0x11A and Register 0x11B)
Bits[13:0]—Initial DC I[13:0]
When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
QEC Initial DC Q (Register 0x11C and Register 0x11D)
Bits[13:0]—Initial DC Q[13:0]
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When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
NSR Control (Register 0x11E)
Bits[7:3]—Open
Bits[2:1]—Noise Shaping Mode
These bits select the mode of the noise shaping requantizer as
shown in Table 18.
Bit 0—NSR On and Off Control
When set high, this bit enables the NSR function.
Table 18.
Setting
00
01
1x
Mode
Low pass mode
High pass mode
Band-pass mode