AD7854 Analog Devices, AD7854 Datasheet - Page 21

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
Self-Calibration Timing
Figure 29 shows the timing for a software full self-calibration.
Here the BUSY line stays high for the full length of the self-
calibration. A self-calibration is initiated by writing to the con-
trol register and setting the STCAL bit to 1. The BUSY line
goes high at the end of the write to the control register, and
BUSY goes low when the full self-calibration is complete after a
time t
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line is triggered high at the end of the write to the
control register and stays high for the full duration of the self-
calibration. The length of time for which BUSY is high depends
on the type of self-calibration that is initiated. Typical values are
given in Table VIII. The timing diagram for the other self-
calibration options is similar to that outlined in Figure 29.
System Calibration Description
System calibration allows the user to remove system errors
external to the AD7854/AD7854L, as well as remove the errors
of the AD7854/AD7854L itself. The maximum calibration
range for the system offset errors is ± 5% of V
system gain errors it is ± 2.5% of V
system gain errors are outside these ranges, the system calibration
algorithm reduces the errors as much as the trim range allows.
Figures 30 through 32 illustrate why a specific type of system
calibration might be used. Figure 30 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be removed by a system offset calibration.
DATA
BUSY
WR
CS
Figure 29. Timing Diagram for Full Self-Calibration
CAL
as show in Figure 29.
Hi-Z
VALID
DATA
t
REF
23
. If the system offset or
Hi-Z
DATA LATCHED INTO
CONTROL REGISTER
REF
t
CAL
, and for the
–21–
Figure 31 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
Finally in Figure 32 both the system offset error and gain error
are removed by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is
adjusted at the top end to account for the system full scale.
SYS OFFSET
SYS OFFSET
V
SYS FULL S.
V
V
MAX SYSTEM FULL SCALE
MAX SYSTEM FULL SCALE
REF
REF
REF
IS ±2.5% FROM V
SYS F.S.
IS ±2.5% FROM V
MAX SYSTEM OFFSET
– 1LSB
MAX SYSTEM OFFSET
– 1LSB
– 1LSB
AGND
AGND
AGND
IS ±5% OF V
IS ±5% OF V
Figure 32. System (Gain + Offset) Calibration
Figure 30. System Offset Calibration
Figure 31. System Gain Calibration
REF
REF
REF
REF
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
SYSTEM OFFSET
SYSTEM OFFSET
SYSTEM OFFSET
FOLLOWED BY
SYSTEM GAIN
CALIBRATION SYS OFFSET
CALIBRATION
CALIBRATION
CALIBRATION
AD7854/AD7854L
V
V
REF
REF
+ SYS OFFSET
+ SYS OFFSET
SYS OFFSET
V
V
SYS FULL S.
MAX SYSTEM FULL SCALE
MAX SYSTEM FULL SCALE
V
MAX SYSTEM FULL SCALE
REF
REF
REF
IS ±2.5% FROM V
IS ±2.5% FROM V
SYS F.S.
IS ±2.5% FROM V
MAX SYSTEM OFFSET
– 1LSB
– 1LSB
– 1LSB
MAX SYSTEM OFFSET
AGND
AGND
AGND
IS ±5% OF V
IS ±5% OF V
REF
REF
REF
REF
REF
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE