AD7854 Analog Devices, AD7854 Datasheet - Page 23

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
PARALLEL INTERFACE
Reading
The timing diagram for a read cycle is shown in Figure 35. The
CONVST and BUSY signals are not shown here as the read
cycle may occur while a conversion is in progress or after the
conversion is complete.
The HBEN signal is low for the first read and high for the sec-
ond read. This ensures that it is the lower 12 bits of the 16-bit
word are output in the first read and the 8 MSBs of the 16-bit
word are output in the second read. If required, the HBEN
signal may be high for the first read and low for the second
read to ensure that the high byte is output in the first read
and the lower byte in the second read. The CS and RD sig-
nals are gated together internally and level triggered active
low. Both CS and RD may be tied together as the timing speci-
fication for t
after both CS and RD go low. The RD rising edge should be
used to latch the data by the user and after a time t
lines will go into their high impedance state.
In Figure 35, the first read outputs the 12 LSBs of the 16-bit
word on pins DB0 to DB11 (DB0 being the LSB of the 12-bit
read). The second read outputs the 8 MSBs of the 16-bit word
on pins DB0 to DB7 (DB0 being the LSB of the 8-bit read). If the
system has a 12-bit or a 16-bit data bus, only one read operation
is necessary to obtain the 12-bit conversion result (12 bits are
output in the first read). A second read operation is not required.
If the system has an 8-bit data bus then two reads are needed.
Pins DB0 to DB7 should be connected the 8-bit data bus. Pins
DB8 to DB11 should be tied to DGND or DV
resistors. With this arrangement, HBEN is pulled low for the
first read and the 8 LSBs of the 16-bit word are output on pins
DB0 to DB7 (data on pins DB8 to DB11 will be ignored).
HBEN is pulled high for the second read and now the 8 MSBs
of the 16-bit word are output on pins DB0 to DB7.
In the case where the AD7854/AD7854L is operated as a read-
only ADC, the WR pin can be tied permanently high. The read
operation need only consist of one read if the system has a 12-
bit or a 16-bit data bus.
When both the CS and RD signals are tied permanently low a
different timing arrangement results, as shown in Figure 36.
Here the data is output a time t
BUSY signal. This allows the falling edge of BUSY to be used
for latching the data. Again if HBEN is low during the conver-
sion the 12 LSBs of the 16-bit word will be output on pins DB0
Figure 35. Read Cycle Timing Diagram Using CS and RD
HBEN
DATA
RD
CS
5
and t
t
6
5
t
are both 0 ns min. The data is output a time t
8
t
t
t
3
8
3
= 15ns MIN,
= 50ns MAX,
VALID
DATA
t
7
t
4
20
t
4
t
9
t
t
6
= 5ns MIN,
9
before the falling edge of the
= 5/40ns MIN/MAX,
t
10
t
5
t
=
3
t
6
VALID
DATA
= 0ns MIN,
DD
t
10
via 10 kΩ
= 70ns MIN
9
the data
t
4
8
–23–
to DB11. Bringing HBEN high causes the 8 MSBs of the 16-bit
word to be output on pins DB0 to DB7. Note that with this
arrangement the data lines are always active.
Writing
The timing diagram for a write cycle is shown in Figure 37. The
CONVST and BUSY signals are not shown here as the write
cycle may occur while a conversion is in progress or after the
conversion is complete.
To write a 16-bit word to the AD7854/AD7854L, two 8-bit
writes are required. The HBEN signal must be low for the first
write and high for the second write. This ensures that it is the
lower 8 bits of the 16-bit word are latched in the first write and
the 8 MSBs of the 16-bit word are latched in the second write.
For both write operations the 8 bits of data should be present on
pins DB0 to DB7 (DB0 being the LSB of the 8-bit write). Any
data on pins DB8 to DB11 is ignored when writing to the device.
The CS and WR signals are gated together internally. Both CS
and WR may be tied together as the timing specification for t
and t
of WR. The data needs to be set up a time t
rising edge and held for a time t
Resetting the Parallel Interface
If random data has been inadvertently written to the test regis-
ter, it is necessary to write the 16-bit word 0100 0000 0000
0010 (in two 8-bit bytes) to restore the test register to its
default value.
CONVST
Figure 36. Read Cycle Timing Diagram with CS and RD
Tied Low
HBEN
DATA
HBEN
BUSY
DATA
WR
CS
14
are both 0 ns min. The data is latched on the rising edge
t
OLD DATA VALID
2
Figure 37. Write Cycle Timing Diagram
t
1
t
11
t
ON PINS DB0 TO DB11
t
13
CONVERT
t
t
CONVERSION IS INITIATED ON THIS EDGE
t
11
15
18
= 0ns MIN,
= 70ns MIN,
t
15
(DB0–DB11)
NEW DATA
t
t
t
VALID
16
DATA
1
19
VALID
= 100ns MIN,
=
t
17
t
t
20
17
12
t
AD7854/AD7854L
16
t
= 70ns MIN,
= 5ns MIN,
14
after the WR rising edge.
t
= 10ns MIN,
12
t
(DB8–DB11)
ON PINS DB0 TO DB7
10
NEW DATA
t
t
19
21
VALID
t
20
t
11
= 70ns MIN,
t
t
13
21
t
16
17
=
=
t
(DB0–DB11)
t
= 5ns MIN
NEW DATA
14
t
before the WR
22
t
22
VALID
20
VALID
DATA
= 0ns MIN,
= 60ns MAX
t
12
(DB8–DB11)
NEW DATA
VALID
13