AD7714 Analog Devices, AD7714 Datasheet - Page 7

• Manufacturer Part Number: AD7714
• Manufacturer: Analog Devices

Specifications of AD7714

• Resolution (bits): 24bit
• # Chan: 5
• Sample Rate: 19.2kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
Read Operation
t
t
t
t
t
t
t
t
Write Operation
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
REV. C
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
See Figures 6 and 7. Timing applies for all grades.
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
The AD7714 is production tested with f
SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
CLKIN
CLK IN LO
CLK IN HI
DRDY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
draw higher current than specified and possibly become uncalibrated.
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
should be taken that subsequent reads do not occur close to the next output update.
6
7
TO OUTPUT
3, 4
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
PIN
50pF
Limit at T
(A, Y Versions)
400
2.5
0.4
0.4
500 t
100
100
0
0
0
80
100
100
100
0
10
60
100
100
0
30
20
100
100
0
t
t
CLK IN
CLK IN
CLK IN
CLKIN
I
I
SINK
SOURCE
MIN
at 2.4576 MHz (1 MHz for some I
(800 A AT DV
, T
100 A AT DV
1, 2
(200 A AT DV
100 A AT DV
MAX
+1.6V
(AV
Logic 1 = DV
DD
DD
DD
= +3.3V)
= DV
= +5V
DD
DD
Units
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
= +5V
= +3.3V)
DD
DD
= +2.7 V to +5.25 V; AGND = DGND = 0 V; f
unless otherwise noted.)
–7–
DD
tests). It is guaranteed by characterization to operate at 400 kHz.
Model
AD7714AN-5
AD7714AR-5
AD7714ARS-5
AD7714AN-3
AD7714AR-3
AD7714ARS-3
AD7714YN
AD7714YR
AD7714YRU
AD7714AChips-5
AD7714AChips-3
EVAL-AD7714-5EB 5 V
EVAL-AD7714-3EB 3 V
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
Conditions/Comments
Master Clock Frequency: Crystal/Resonator or Externally
Supplied
For Specified Performance
Master Clock Input Low Time. t
Master Clock Input High Time
DRDY High Time
SYNC Pulsewidth
RESET Pulsewidth
DRDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time
DV
DV
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Active Edge Hold Time
Bus Relinquish Time after SCLK Active Edge
DV
DV
SCLK Active Edge to DRDY High
CS Falling Edge to SCLK Active Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
SCLK Active Edge to Data Valid Delay
Data Valid to SCLK Edge Setup Time
DD
DD
DD
DD
= +5 V
= +3 V
= +5 V
= +3 V
ORDERING GUIDE
AV
Supply
5 V
5 V
5 V
3 V
3 V
3 V
3 V/5 V
3 V/5 V
3 V/5 V
5 V
3 V
DD
) and timed from a voltage level of 1.6 V.
DD
CLKIN
OL
or V
= 2.5 MHz; Input Logic 0 = 0 V,
Evaluation Board
Temperature
Range
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +105 C
–40 C to +105 C
–40 C to +105 C
–40 C to +85 C
–40 C to +85 C
Evaluation Board
CLK IN
OH
5, 8
limits.
= 1/f
5
CLK IN
AD7714
5
5
5
5
Package
Option*
N-24
R-24
RS-28
N-24
R-24
RS-28
N-24
R-24
RU-24
Die
Die
2