AD9751 Analog Devices, AD9751 Datasheet - Page 13

• Manufacturer Part Number: AD9751
• Manufacturer: Analog Devices

Specifications of AD9751

• Resolution (bits): 10bit
• Dac Update Rate: 300MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

INTERLEAVED (2 ) MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2× the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1× clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1× clock, the setup-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2× clock. With the PLL disabled,
a load-dependent delayed version of the 1× clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
Updates to the data at input Ports 1 and 2 should be synchro-
nized to the specific rising edge of the external 2× clock that
corresponds to the rising edge of the 1× internal clock, as shown
in Figure 11. To ensure synchronization, a Logic 1 must be
momentarily applied to the RESET pin. Doing this and return-
ing RESET to Logic 0 brings the 1× clock at PLLLOCK to a
Logic 1. On the next rising edge of the 2× clock, the 1× clock will
go to Logic 0. On the second rising edge of the 2× clock, the 1×
clock (PLLLOCK) will again go to Logic 1, as well as update
the data in both of the input latches. The details of this are
shown in Figure 12.
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2×
clock. RESET going low must occur either at least t
the rising edge of the 2× clock or t
case, the immediately occurring CLK rising edge will cause
PLLLOCK to go low. In the second case, the next CLK rising
edge will toggle PLLLOCK.
REV. C
Figure 11. Timing Requirements, Interleaved (2 × ) Mode
with PLL Disabled
@ PLLLOCK
Figure 12. Reset Function Timing with PLL Disabled
EXTERNAL
EXTERNAL
INTERNAL
DATA IN
DELAYED
PORT 1
PORT 2
1
1
2
CLK
CLK
CLK
EXTERNAL
2
PLLLOCK
CLOCK
RESET
DATA X
DATA Y
I
t
OUTA
S
ON THESE EDGES
INPUT LATCHES
t
t
OR I
t
H
DATA ENTERS
LPW
D
t
RS
OUTB
= 0.2ns
RH
t
PD
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
ns afterwards. In the first
DATA X
t
RH
= 1.2ns
t
PD
RS
DATA Y
ns before
–13–
NONINTERLEAVED MODE WITH PLL DISABLED
If the data at only one port is required, the AD9751 interface
can operate as a simple double-buffered latch with no interleaving.
On the rising edge of the 1× clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time t
represents the AD9751 timing in this mode.
DAC TRANSFER FUNCTION
The AD9751 provides complementary current outputs, I
and I
I
I
current output appearing at I
both the input code and I
where DAC CODE = 0 to 1023 (i.e., decimal representation).
As mentioned previously, I
current, I
V
where
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be directly connected to matching resistive loads, R
that are tied to analog common, ACOM. Note that R
represent the equivalent load resistance seen by I
as would be the case in a doubly terminated 50 Ω or 75 Ω cable.
The single-ended voltage output appearing at the I
I
Note that the full-scale values of V
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
Substituting the values of I
expressed as
OUTFS
OUTB
OUTB
Figure 13. Timing Requirements, Noninterleaved Mode
with PLL Disabled
REFIO
V
V
V
V
(
I
I
I
OUTB
I
, the complementary output, provides no current. The
PD
R
OUTA
OUTB
, when all bits are high (i.e., DAC CODE = 1023) while
REF
nodes is simply
OUTFS
OUTA
OUTB
, and external resistor R
DIFF
DIFF
LOAD
PORT 1 OR
1
later, the DAC output reflects this change. Figure 13
DATA IN
REF
. I
=
PORT 2
CLOCK
=
=
=
=
=
=
V
OUTA
=
, which is nominally set by a reference voltage,
(
{
(
(
R
REFIO
I
I
1023
I
DAC CODE
(
32
OUTA
OUTB
OUTA
2
SET
DAC CODE
provides a near full-scale current output,
×
)
I
OUTA
I
−
×
R
×
×
−
REF
t
V
SET
S
DAC CODE
R
R
I
REFIO
OUTB
OR I
LOAD
LOAD
OUTFS
t
OUTFS
OUTA
t
OUTB
H
LPW
)
1024
OUTA
×
SET
, and can be expressed as
−
, I
R
is a function of the reference
1023 1024
. It can be expressed as
LOAD
OUTB
)
and I
OUTA
×
)
I
1024
, and I
)
OUTFS
OUTB
and V
XX
×
t
PD
REF
is a function of
}
I
OUTB
OUTFS
×
, V
AD9751
DATA OUT
PORT 1 OR
PORT 2
OUTA
OUTA
OUTA
DIFF
should not
LOAD
and I
or I
can be
and
OUTA
OUTB
LOAD
may
OUTB
(3)
(4)
(7)
(8)
(1)
(2)
(5)
(6)
,