AD9751 Analog Devices, AD9751 Datasheet - Page 18

• Manufacturer Part Number: AD9751
• Manufacturer: Analog Devices

Specifications of AD9751

• Resolution (bits): 10bit
• Dac Update Rate: 300MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9751
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well
as power supply bypassing and grounding, to ensure optimum
performance. Figures 34 to 41 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9751 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise occurs over the spectrum from tens of kHz to sev-
eral MHz. The PSRR versus frequency of the AD9751 AVDD
supply over this frequency range is shown in Figure 25.
AD9751
Figure 24. Unipolar Buffered Voltage Output
85
80
75
70
65
60
55
50
45
40
Figure 25. Power Supply Rejection Ratio
0
I
I
OUTA
OUTB
2
200
4
OUTFS
FREQUENCY (MHz)
. AC noise on the dc supplies is
6
200
C
R
OPT
FB
8
V
OUT
10
= I
OUTFS
12
R
FB
–18–
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of modu-
lating the internal switches, and therefore the output current.
The voltage noise on AVDD is thus added in a nonlinear man-
ner to the desired I
switches, PSRR is very code-dependent. This can produce a
mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs occurs when the full-scale current is
directed toward that output. As a result, the PSRR measure-
ment in Figure 25 represents a worst-case condition in which
the digital inputs remain static and the full-scale output current
of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for the
sake of simplicity (i.e., ignore harmonics), all of this noise is
concentrated at 250 kHz. To calculate how much of this undes-
ired noise will appear as current noise superimposed on the
DAC’s full-scale current, I
in dB using Figure 25 at 250 kHz. To calculate the PSRR for a
given R
A/V to V/V, adjust the curve in Figure 25 by the scaling factor
20
reduced by 34 dB, i.e., PSRR of the DAC at 250 kHz, which is
85 dB in Figure 25, becomes 51 dB V
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9751 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a sys-
tem. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
Figure 26. Differential LC Filter for a Single 3.3 V Application
TTL/CMOS
CIRCUITS
POWER SUPPLY
log (R
LOGIC
LOAD
3.3V
LOAD
, such that the units of PSRR are converted from
). For instance, if R
OUT
FERRITE
BEADS
. Due to the relative different size of these
OUTFS
ELECT.
100 F
, one must determine the PSRR
10 F–22 F
LOAD
TANT.
OUT
is 50 Ω, the PSRR is
/V
IN
.
0.1 F
CER.
REV. C
AVDD
ACOM