AD660 Analog Devices, AD660 Datasheet - Page 14

• Manufacturer Part Number: AD660
• Description: Monolithic 16-Bit Serial/Byte DACPORT
• Manufacturer: Analog Devices

Specifications of AD660

• Resolution (bits): 16bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Ser

AD660
DIGITAL CIRCUIT DETAILS
The AD660 has several dual-use pins that allow flexible opera-
tion while maintaining the lowest possible pin count and
consequently the smallest package size. The user should,
therefore, pay careful attention to the following information
when applying the AD660.
Data can be loaded into the AD660 in serial or byte mode,
described as follows.
Serial mode operation is enabled by bringing SER (Pin 17) low.
This changes the function of DB0 (Pin 12) to that of the serial
input pin, SIN. It also changes the function of DB1 (Pin 11) to
a control input that tells the AD660 whether the serial data is
going to be loaded MSB or LSB first.
In serial mode, HBE and LBE are effectively disabled except
for the dual function of LBE , which is to control whether the
asynchronous clear function goes to unipolar or bipolar zero.
(A low on LBE , when CLR is strobed, sends the DAC output
to unipolar zero, a high to bipolar zero.) The AD660 does not
recognize the status of HBE when in serial mode.
Data is clocked into the input register on the rising edge of CS ,
as shown in Figure 3. The data then resides in the first rank latch
and can be loaded into the DAC latch by taking LDAC high.
This causes the DAC to change to the appropriate output value.
It should be noted that the CLR function clears the DAC latch
but does not clear the first rank latch. Therefore, the data that
was previously residing in the first rank latch can be reloaded
simply by bringing LDAC high after the event that necessitated
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CLR to be strobed has ended. Alternatively, new data can be
loaded into the first rank latch if desired.
The serial out pin (S
together in multiDAC applications to minimize the number of
isolators being used to cross an intrinsic safety barrier. The first
rank latch acts like a 16-bit shift register, and repeated strobing
of CS shifts the data out through S
Each DAC in the chain requires its own LDAC signal unless all
of the DACs are to be updated simultaneously.
Byte mode operation is enabled simply by keeping SER high,
which configures DB0 to DB7 as data inputs. In this mode, HBE
and LBE are used to identify the data as either the high byte or
the low byte of the 16-bit input word. (The user can load the
data, in any order, into the first rank latch.) As in the serial mode
case, the status of LBE , when CLR is strobed, determines whether
the AD660 clears to unipolar or bipolar zero. Therefore, when in
byte mode, the user must take care to set LBE to the desired
status before strobing CLR . (In serial mode the user can simply
hardware LBE to the desired state.)
Note that CS is edge triggered. HBE , LBE , and LDAC are level
triggered.
OUT
) can be used to daisy-chain several DACs
OUT
and into the next DAC.