ADA4891-3 Analog Devices, ADA4891-3 Datasheet - Page 17

• Manufacturer Part Number: ADA4891-3
• Description: Low Cost CMOS, High Speed, Rail-to-Rail Amplifier (Triple)
• Manufacturer: Analog Devices

Specifications of ADA4891-3

• -3db Bandwidth: 220MHz
• Slew Rate: 170V/µs
• Vos: 2.5mV
• Ib: 2pA
• # Opamps Per Pkg: 3
• Input Noise (nv/rthz): 9nV/rtHz
• Vcc-vee: 2.7V to 5.5V
• Isy Per Amplifier: 4.4mA
• Packages: Mini-SO,SOP

DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation. The ADA4891-1/ADA4891-2 are
used to demonstrate this effect (see Figure 55 and Figure 56).
–100
–0.1
–0.2
–0.3
–10
100
0.2
0.1
–2
–4
–6
–8
0
8
6
4
2
0
0
0.1
Figure 55. Closed-Loop Frequency Response, C
0.1
V
G = +2
R
R
V
V
V
G = +1
R
C
50mV/DIV
S
F
L
OUT
S
OUT
L
L
Figure 54. 0.1 dB Gain Flatness vs. C
= 5V
= 604Ω
= 150Ω
Figure 56. 200 mV Step Response, C
= 5V
= 1kΩ
= 6.8pF
= 2V p-p
= 200mV p-p
ADA4891-1/ADA4891-2
ADA4891-1/ADA4891-2
ADA4891-1/ADA4891-2
1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
C
F
10
= 3.3pF
10
F
L
C
, V
= 6.8 pF,
F
S
= 0pF
= 5 V,
100
L
= 6.8 pF,
V
G = +1
R
C
C
S
L
L
50ns/DIV
F
= 5V
= 1kΩ
= 6.8pF
= 1pF
100
Rev. C | Page 17 of 24
ADA4891-1/ADA4891-2/ADA4891-3/ADA4891-4
These four methods minimize the output capacitive loading effect.
•
•
•
•
Figure 57 shows the effect of using a snub resistor (R
the peaking in the worst-case frequency response (gain of +1).
Using R
that the closed-loop gain is reduced by 0.9 dB due to attenuation
at the output. R
an acceptable level of peaking and closed-loop gain, as shown in
Figure 57.
Figure 58 shows that the transient response is also much improved
by the snub resistor (R
Figure 57. Closed-Loop Frequency Response with Snub Resistor, C
Reducing the output resistive load. This pushes the pole
further away and, therefore, improves the phase margin.
Increasing the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitive loads with less peaking.
Adding a parallel capacitor (C
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by the
capacitive load and the output impedance of the amplifier.
See the Effect of R
more information.
Placing a small value resistor (R
to isolate the load capacitor from the output stage of the
amplifier.
–100
–10
100
–2
–4
–6
–8
S
8
6
4
2
0
0
Figure 58. 200 mV Step Response, C
= 100 Ω reduces the peaking by 3 dB, with the trade-off
0.1
200mV
V
V
G = +1
R
C
50mV/DIV
STEP
S
OUT
L
L
= 5V
= 1kΩ
= 6.8pF
V
IN
S
= 200mV p-p
can be adjusted from 0 Ω to 100 Ω to maintain
50Ω
S
1
F
= 100 Ω) compared to that of Figure 56.
on 0.1 dB Gain Flatness section for
R
R
S
FREQUENCY (MHz)
S
= 100Ω
= 0Ω
R
R
S
L
F
10
) with R
S
) in series with the output
L
= 6.8 pF, R
C
L
OUT
F
, from −IN to the
100
S
V
G = +1
R
C
R
= 100 Ω
S
L
L
S
50ns/DIV
S
) on reducing
= 5V
= 1kΩ
= 6.8pF
= 100Ω
L
= 6.8 pF