ADA4817-1 Analog Devices, ADA4817-1 Datasheet - Page 18

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ADA4817-1

Manufacturer Part Number
ADA4817-1
Description
Low Noise, 1 GHz FastFET Op Amps
Manufacturer
Analog Devices
Datasheet

Specifications of ADA4817-1

-3db Bandwidth
1.05GHz
Slew Rate
870V/µs
Vos
400µV
Ib
2pA
# Opamps Per Pkg
1
Input Noise (nv/rthz)
4nV/rtHz
Vcc-vee
5V to 10V
Isy Per Amplifier
21mA
Packages
CSP,SOIC

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ADA4817-1/ADA4817-2
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets
up leakage currents through the PCB insulator, for example, 1 V/
100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and should completely
surround the input leads on all sides (above and below)
while using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon® or ceramic, can be necessary in some instances.
Rev. A | Page 18 of 28
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, in turn increasing the gain of the amplifier, causing
peaking of the frequency response or even oscillations if severe
enough. It is recommended that the external passive components
connected to the input pins be placed as close as possible to the
inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a small distance from the input pins on
all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
the output signal traces should not be parallel with the inputs.
In addition, the input traces should not be close to each other. A
minimum of 7 mils between the two inputs is recommended.

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