ADA4857-2 Analog Devices, ADA4857-2 Datasheet - Page 16

• Manufacturer Part Number: ADA4857-2
• Description: Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp
• Manufacturer: Analog Devices

Specifications of ADA4857-2

• -3db Bandwidth: 750MHz
• Slew Rate: 2.8kV/µs
• Vos: 2mV
• Ib: 2µA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 4.4nV/rtHz
• Vcc-vee: 4.5V to 10.5V
• Isy Per Amplifier: 5.5mA
• Packages: CSP

ADA4857-1/ADA4857-2
APPLICATIONS INFORMATION
POWER-DOWN OPERATION
The PD pin is used to power down the chip, which reduces the
quiescent current and the overall power consumption. It is low
enabled, which means that the chip is on with full power when
the PD pin input voltage is low (see Table 8). Note that PD does not
put the output in a high-Z state, which means that the ADA4857
should not be used as a multiplexer.
Table 8. PD Operation Table Guide
Condition
Enabled
Powered down
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; V
Gain
+1
+2
+5
+10
R
0/100
0/0
0/0
0/0
S
(Ω) (CSP/SOIC)
±5 V
≤+0.8 V
≥+3 V
R
0
499
499
499
F
(Ω)
Supply Voltage
R
N/A
499
124
56.2
±2.5 V
≤−1.7 V
≥+0.5 V
G
(Ω)
−3 dB SS BW (MHz)
(CSP/SOIC)
850/750
360/320
90/89
43/40
+5 V
≤+0.8 V
≥+3 V
Rev. B | Page 16 of 20
Slew Rate (V/μs),
V
2350
1680
516
213
OUT
CAPACITIVE LOAD CONSIDERATIONS
When driving a capacitive load using the SOIC package, R
used to reduce the peaking (see Figure 47). An optimum resistor
value of 40 Ω is found to maintain the peaking within 1 dB for
any capacitive load up to 40 pF.
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 9 provides a useful reference for determining various gains
and associated performance. R
their contribution to the overall noise performance of the amplifier.
= 2 V Step
ADA4857 Voltage
Noise (nV/√Hz), RTO
4.4
8.8
22.11
43.47
S
= ±5 V, T
F
and R
A
= 25°C, R
G
are kept low to minimize
L
Total System
Noise (nV/√Hz), RTO
4.49
9.89
23.49
45.31
= 1 kΩ, R
Data Sheet
T
= 49.9 Ω
SNUB
is