ADA4857-2 Analog Devices, ADA4857-2 Datasheet - Page 6

• Manufacturer Part Number: ADA4857-2
• Description: Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp
• Manufacturer: Analog Devices

Specifications of ADA4857-2

• -3db Bandwidth: 750MHz
• Slew Rate: 2.8kV/µs
• Vos: 2mV
• Ib: 2µA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 4.4nV/rtHz
• Vcc-vee: 4.5V to 10.5V
• Isy Per Amplifier: 5.5mA
• Packages: CSP

ADA4857-1/ADA4857-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
for device soldered in circuit board for surface-mount packages.
Table 4.
Package Type
8-Lead SOIC
8-Lead LFCSP
16-Lead LFCSP
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4857 is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the properties of the plastic change. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the ADA4857. Exceeding a junction temperature of
175°C for an extended period can result in changes in silicon
devices, potentially causing degradation or loss of functionality.
JA
is specified for the worst-case conditions, that is, θ
θ
115
94.5
68.2
JA
Rating
11 V
See Figure 4
−V
±V
−V
−65°C to +125°C
−40°C to +125°C
300°C
150°C
S
S
S
θ
15
34.8
19
+ 0.7 V to +V
JC
JA
is specified
Unit
°C/W
°C/W
°C/W
S
J
) on
− 0.7 V
Rev. B | Page 6 of 20
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
die due to the ADA4857 drive at the output. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
RMS output voltages should be considered. If R
to −V
V
worst case, when V
In single-supply operation with R
case is V
Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduces θ
Figure 4 shows the maximum power dissipation in the package
vs. the ambient temperature for the SOIC and LFCSP packages
on a JEDEC standard 4-layer board. θ
ESD CAUTION
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
S
× I
P
P
P
S
OUT
D
D
, as in single-supply operation, the total drive power is
D
3.0
2.5
2.0
1.5
1.0
0.5
= Quiescent Power + (Total Drive Power − Load Power)
0
=
=
OUT
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
. If the rms signal levels are indeterminate, consider the
(
(
V
V
= V
S
S
×
×
I
I
S
/2.
S
S
) (
)
+
ADA4857-1 (LFCSP)
OUT
+
S
).




V
AMBIENT TEMPERATURE (°C)
V
= V
2
S
R
S
4 /
L
×
S
)
2
/4 for R
V
R
OUT
L
ADA4857-1 (SOIC)




L
ADA4857-2 (LFCSP)
–
L
referenced to −V
JA
JA
to midsupply.
V
.
values are approximations.
OUT
R
D
L
) is the sum of the
2
Data Sheet
L
S
) times the
is referenced
S
, the worst
JA
.