TDA744813TR STMicroelectronics, TDA744813TR Datasheet - Page 5

• Manufacturer Part Number: TDA744813TR
• Description: IC CTLR VOLUME 6CH I/O 20-SOIC
• Manufacturer: STMicroelectronics
• Type: Volume Controlr

Specifications of TDA744813TR

• Applications: Multi-Channels Audio Systems
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8884-2

4
Data transmission from microprocessor to the TDA7448 and vice versa takes place through the 2 wires I
terface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
4.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig. 9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
4.4 Acknowledge
The master ( P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The
peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 8. Data Validity on the I
Figure 9. Timing Diagram of I
Figure 10. Acknowledge on the I
I
2
C BUS INTERFACE
SCL
SDA
SDA
SCL
SDA
SCL
START
START
2
CBUS
2
CBUS
MSB
2
1
CBUS
STABLE, DATA
DATA LINE
VALID
2
D99AU1033
D99AU1032
ALLOWED
CHANGE
DATA
3
7
8
ACKNOWLEDGMENT
FROM RECEIVER
STOP
D99AU1031
I
2
9
CBUS
TDA7448
2
C BUS in-
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