ADUC816 Analog Devices, ADUC816 Datasheet - Page 53

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

REV. A
TCON: Timer/Counter 0 and 1 Control Register
SFR Address
Power-On Default Value
Bit Addressable
NOTE
1
Bit
7
6
5
4
3
2
1
0
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8Chex, 8Ahex respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8Dhex, 8Bhex respectively.
These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
T
F
1
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
T
R
1
88H
00H
Yes
Description
Timer 1 Overflow Flag.
Timer 1 Run Control Bit.
Timer 0 Overflow Flag.
Timer 0 Run Control Bit.
External Interrupt 1 (INT1) Flag.
ing on bit IT1 state.
rupt was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
External Interrupt 0 (INT0) Flag.
ing on bit IT0 state.
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
T
by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depend-
by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depend-
by hardware on a timer/counter 1 overflow.
by user to turn on timer/counter 1.
by hardware on a timer/counter 0 overflow.
by user to turn on timer/counter 0.
by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
F
0
by hardware when the when the PC vectors to the interrupt service routine only if the inter-
by hardware when the PC vectors to the interrupt service routine only if the interrupt was
by hardware when the Program Counter (PC) vectors to the interrupt service routine.
by user to turn off timer/counter 1.
by hardware when the PC vectors to the interrupt service routine.
by user to turn off timer/counter 0.
by software to specify level-sensitive detection (i.e., zero level).
by software to specify level-sensitive detection (i.e., zero level).
Table XXIV. TCON SFR Bit Designations
T
R
0
I
E
1
1
I
T
1
1
I
E
0
1
I
T
0
1