ADUC816 Analog Devices, ADUC816 Datasheet - Page 7

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

REV. A
Parameter
POWER REQUIREMENTS (continued)
NOTES
10
11
12
13
14
15
16
17
Specifications subject to change without notice
1
2
3
4
5
6
7
8
9
In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A
Pins configured in I
Pins configured in I
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700 Kcycles.
Retention lifetime equivalent at junction temperature (T
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
DV
Temperature Range –40°C to +85°C.
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
The primary ADC is factory-calibrated at 25°C with AV
cantly different from these, an Internal Full-Scale Calibration will restore this error to this level.
Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
The auxiliary ADC is factory-calibrated at 25°C with AV
will remove this error altogether.
DAC linearity and AC Specifications are calculated using:
Gain Error is a measure of the span error of the DAC.
In general terms, the bipolar input voltage range to the primary ADC is given by Range
V
RN = decimal equivalent of RN2, RN1, RN0, e.g., V
In unipolar mode the effective range is 0 V to 1.28 V in our example.
1.25 V is used as the reference voltage to the ADC when internal V
range is still –V
will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.
Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON,
PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR.
Power Supply Currents Normal Mode
Power Supply Currents Idle Mode
Power Supply Currents Power-Down Mode
Typical Additional Power Supply Currents
REF
reduced code range of 48 to 4095, 0 to V
reduced code range of 48 to 3995, 0 to V
DD
DV
AV
DV
AV
DV
AV
DV
AV
DV
AV
DV
(AI
PSM Peripheral
Primary ADC
Auxiliary ADC
DAC
Dual Current Sources
= REFIN(+) to REFIN(–) voltage and V
power supply current will typically increase by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Current
Current
Current
Current
Current
and DI
Current
Current
Current
Current
Current
Current
REF
to +V
2
2
C-compatible mode or SPI mode, pins configured as digital inputs during this test.
C-compatible mode only.
DD
)
REF
; however, the negative voltage is limited to –30 mV.
REF
DD
16, 17
.
REF
16, 17
= 1.25 V when internal ADC V
16, 17
REF
J
DD
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
DD
= 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the Range
= DV
= DV
ADuC816BS
4
2.1
170
15
8
170
1.2
750
140
2
1
140
50
20
1
20
5
50
1
500
150
400
DD
DD
REF
= 5 V yielding this full-scale error. If user power supply or temperature conditions are signifi-
= 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively.
GND
– 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar
REF
Unit
mA max
mA max
μA max
mA max
mA max
μA max
mA max
μA typ
μA typ
mA typ
mA typ
μA typ
μA max
μA max
μA max
μA max
μA typ
μA typ
mA typ
μA typ
μA typ
μA typ
is selected.
ADC
= ± (V
REF
Test Conditions/Comments
DV
DV
AV
DV
DV
AV
DV
DV
Measured @ AV
DV
DV
Measured at AV
Core CLK = 1.57 MHz or 12.58 MHz
DV
DV
Measured at AV
DV
DV
Core CLK = 1.57 MHz, AV
2
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
RN
)/125, where:
= 5.25 V, Core CLK = 1.57 MHz
= 5.25 V, Core CLK = 12.58 MHz
= 2.7 V to 3.6 V, Osc. On, TIC On
= 4.75 V to 5.25 V, Core CLK = 1.57 MHz
= 2.7 V to 3.6 V, Core CLK = 1.57 MHz
= 4.75 V to 5.25 V, Core CLK = 12.58 MHz
= 2.7 V to 3.6 V, Core CLK = 12.58 MHz
= 4.75 V to 5.25 V, Core CLK = 1.57 MHz
= 2.7 V to 3.6 V, Core CLK = 1.57 MHz
= 4.75 V to 5.25 V, Core CLK = 12.58 MHz
= 2.7 V to 3.6 V, Core CLK = 12.58 MHz
= 4.75 V to 5.25 V, Osc. On, TIC On
= 4.75 V to 5.25 V, Osc. Off
= 2.7 V to 3.6 V, Osc. Off
ADC
= ± 1.28 V.
DD
DD
DD
= 5.25 V, Core CLK = 12.58 MHz
= 5.25 V, Core CLK = 1.57 MHz
= 5.25 V, Osc. On or Osc. Off
DD
= DV
DD
= 5 V