E-TDA7590TR STMicroelectronics, E-TDA7590TR Datasheet - Page 34

• Manufacturer Part Number: E-TDA7590TR
• Description: IC DSP SPEECH/AUDIO 144-TQFP
• Manufacturer: STMicroelectronics
• Type: Signalr

Specifications of E-TDA7590TR

• Applications: Speech Recognition
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP Exposed Pad, 144-eTQFP, 144-HTQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix 1
34/42
;------------------------------------------------------------------------
;
;------------------------------------------------------------------------
init_codec
;------------------------------------------------------------------------
;
;------------------------------------------------------------------------
; The receiver and transmitter control/status register are configured the same for simplicity only.
; Master mode , 24-bit word-size , MSB first , Low word clock = left word , Neg bit-clk polarity ,
; Non i2s format ,
init_sai
;------------------------------------------------------------------------
; Enable gpios for HI
;------------------------------------------------------------------------
;------------------------------------------------------------------------
; Initialize ESSI0
;------------------------------------------------------------------------
init_essi
Enable_pins
;------------------------------------------------------------------------
movep
bset
movep
IF 1
Initialise CODEC
movep
Initialise SAI
movep
movep
bset
bset
bset
bset
ENDIF
IF 1
movep #$181801,x:M_CRA0 ; cra0_addr, 24'b010110000001100000011110
movep #$fc113e,x:M_CRB0 ; crb0_addr, 24'b111111000001010100111110
move
movep x:M_CRB0,b1
or
movep #$00003f,x:M_PCRC ; // ALL Pins are ESSI.
rep
nop
#GPIO0_DIR,x:GPIOCTRL
#GPIO0_DIR,x:GPIODIR
#GPIO1_DIR,x:GPIOCTRL
#GPIO1_DIR,x:GPIODIR
#$01c000,x0
x0,b1
#$05
#INIT_PLL_FCR,x:PLL_FCR
#FRACEN,x:<<PLL_CSR
#INIT_PLL_CLKCTL,x:PLL_CLKCTL
#INIT_CODEC_CSR,x:CODEC_CSR
#INIT_SAI_TCS,y:SAI_TCS
#INIT_SAI_RCS,y:SAI_RCS
(For 32-bit words) First bit x 8 , Interrupts enabled.
; The divider control is set to 1 (2 words per frame)
; for Normal mode, bits are left aligned to bit 23.
; length is set to 24 bits.PM = 1 -> Fcore/4.
; The receive exception and transmit exception interrupts
; are enabled as are receive last slot and transmit last
; slot. It is set in the synchronous normal mode. Data and
; frame sync are clocked out on the rising edge of the clock.
; Frame sync polarity is positive and occurs together with the
; the first bit of data from the first slot.
; first. SC2 o/p SC1 o/p SC0 o/p
;
;
;
; check that all pins are enabled
// Enable TX2/TX1/TX0 (ESSI 0)
; Setup HI pin for GPIO mode
; Setup GPIO as output
; Setup HI pin for GPIO mode
; Setup GPIO as output
; set fract value.
; enable fractional-n operation.
; setup the clock generation.
; initialise CODEC control/status reg
; initialise transmit control/status reg
; initialise receiver control/status reg
MSB is shifted
Word
TDA7590