MAX4397SCTM+T Maxim Integrated Products, MAX4397SCTM+T Datasheet - Page 16

• Manufacturer Part Number: MAX4397SCTM+T
• Description: IC SW A/V SCART CON 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Switchr

Specifications of MAX4397SCTM+T

• Applications: DVD, Set-Top Boxes, TV
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The TV channel volume control ranges from -56dB to
+6dB in 2dB steps. The VCR volume control settings
are programmable for -6dB, 0dB, and +6dB. These
gain levels are referenced to the application inputs,
where some dividers are present. With the ZCD bit set,
the TV volume control switches only at zero-crossings,
thus minimizing click noise. The TV outputs can bypass
the volume control. Likewise, the monaural output sig-
nal can be processed by the TV volume control or it
can bypass the volume control.
The MAX4397 uses a simple 2-wire serial interface
requiring only two standard microprocessor port I/O
lines. The fast-mode I
allows communication at data rates up to 400kbps or
400kHz. Figure 6 shows the timing diagram of the sig-
nals on the 2-wire interface.
Audio/Video Switch for Dual SCART Connectors
Figure 6. SDA and SCL Signal Timing Diagram
16
SDA
SCL
______________________________________________________________________________________
t
HD
START CONDITION
,
STA
t
LOW
2
C-compatible serial interface
t
R
t
SU
,
DAT
t
F
Digital Section
Volume Control
Serial Interface
t
HD
,
DAT
t
SU
REPEATED START CONDITION
,
STA
The two bus lines (SDA and SCL) must be at logic-high
when the bus is not in use. The MAX4397 is a slave
device and must be controlled by a master device.
Pullup resistors from the bus lines to the supply are
required when push-pull circuitry is not driving the
lines.
The logic level on the SDA line can only change when
the SCL line is low. The start and stop conditions occur
when SDA toggles low/high while the SCL line is high
(see Figure 6). Data on SDA must be stable for the
duration of the setup time (t
high. Data on SDA is sampled when SCL toggles high
with data on SDA stable for the duration of the hold time
(t
A total of nine clock cycles are required to transfer a
byte to the MAX4397. The device acknowledges the
successful receipt of the byte by pulling the SDA line
low during the 9th clock cycle.
HD,DAT
). Note that data is transmitted in an 8-bit byte.
t
HD
,
STA
t
SU
,
SU,DAT
STA
STOP CONDITION
) before SCL goes
t
BUF