PSMN8R0-30YL NXP Semiconductors, PSMN8R0-30YL Datasheet - Page 8

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PSMN8R0-30YL

Manufacturer Part Number
PSMN8R0-30YL
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
PSMN8R0-30YL
Product data sheet
Fig 13. Normalized drain-source on-state resistance
Fig 15. Gate-source voltage as a function of gate
V
a
(V)
1.5
0.5
GS
10
2
1
0
8
6
4
2
0
−60
factor as a function of junction temperature
charge; typical values
0
0
5
6V
24V
60
10
120
15
V
DS
All information provided in this document is subject to legal disclaimers.
Q
003aaf428
= 15V
T
G
j
(nC)
( ° C)
03aa27
180
20
Rev. 2 — 16 May 2011
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
Fig 14. Gate charge waveform definitions
Fig 16. Source (diode forward) current as a function of
(A)
I
S
60
45
30
15
0
source-drain (diode forward) voltage; typical
values
0
V
V
V
V
GS(pl)
DS
GS(th)
GS
0.3
Q
GS1
I
Q
D
PSMN8R0-30YL
T
GS
Q
j
= 150 °C
GS2
0.6
Q
G(tot)
Q
GD
0.9
© NXP B.V. 2011. All rights reserved.
T
j
003aaa508
V
003aaf429
= 25 °C
SD
(V)
1.2
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