ST7232AK1 STMicroelectronics, ST7232AK1 Datasheet - Page 63

• Manufacturer Part Number: ST7232AK1
• Description: 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST7232AK1

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
2. If the OCiE bit is not set, the OCMPi pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 39. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OCiLR register is also written.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMPi are set while the counter value equals
the OCiR register value (see
64). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure 41 on page
CPU
i
R register and the
CPU
Figure 40 on page
/4, f
/2, OCFi and
OC1E
CPU
OCIE
OC2E
OCF1
/8 or in
64).
FOLV2 FOLV1
6. In Flash devices, the TAOC2HR, TAOC2LR
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
registers are "write only" in Timer A. The corre-
sponding event cannot be generated (OCF2 is
forced by hardware to 0).
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
ST7232A
OCMP1
OCMP2
Pin
Pin
63/157
1