ST72215G2 STMicroelectronics, ST72215G2 Datasheet - Page 29
ST72215G2
Manufacturer Part Number
ST72215G2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
Manufacturer
STMicroelectronics
Datasheet
1.ST72104G2.pdf
(141 pages)
Specifications of ST72215G2
Emulation Voltage
5.5 V
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POWER SAVING MODES (Cont’d)
8.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Mapping,” on page
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 "OPTION BYTES" on page 133
more details).
Figure 19. HALT Mode Timing Overview
INSTRUCTION
RUN
HALT
HALT
INTERRUPT
RESET
OR
4096 CPU CYCLE
26) or a RESET. When exiting
DELAY
Figure
Table 5, “Interrupt
20).
VECTOR
FETCH
Figure
RUN
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
19).
for
Figure 20. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
N
HALT INSTRUCTION
WATCHDOG
WDGHALT
Table 5, “Interrupt Mapping,” on page 26
RESET
1
INTERRUPT
Y
1)
3)
ENABLE
4096 CPU CLOCK CYCLE
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
DELAY
RESET
Y
WATCHDOG
DISABLE
2)
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
X
0
1
4)
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