ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 45

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
7.5
7.5.1
Figure 21. Nested interrupt management
Interrupt registers
CPU CC register interrupt bits
Table 15.
Table 16.
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
CPU CC
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Bit Name
5
3
R/W
7
1
I1
I0
Interrupt software priority
Software Interrupt Priority 1
Software Interrupt Priority 0
CPU CC register interrupt bits description
Interrupt software priority levels
11 / 10
R/W
Main
RIM
6
1
IT2
(1)
IT1
R/W
I1
5
Table 18: Dedicated interrupt instruction
IT4
TRAP
R/W
H
4
IT4
IT0
Function
IT3
R/W
I0
3
IT1
Level
High
Low
IT2
10
R/W
N
2
Main
Software
priority
level
Reset value: 111x 1010(xAh)
Table
I1
1
0
0
1
set).
3
3
2
1
3
3
3/0
16) and are
R/W
1
Z
I1
1 1
1 1
0 0
0 1
1 1
1 1
Interrupts
I0
I0
R/W
0
1
0
1
C
0
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