ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 55

• Manufacturer Part Number: ST72521R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72521R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72521xx-Auto
Note:
7.3
Note:
7.4
Figure 19. Concurrent interrupt management
11 / 10
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) will therefore be lost if the clear sequence is executed.
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt/Active Halt” in
interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt
with “exit from Halt mode” capability and it is selected through the same decision process
shown in
If an interrupt that is not able to exit from Halt mode is pending with the highest priority when
exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent and nested management
The following
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
MAIN
RIM
flag is set in the peripheral status registers and if the corresponding enable bit is set in
the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Warning:
Figure
IT2
Figure 19
Figure
18.
A stack overflow may occur without notifying the software of
the failure.
IT1
20. The interrupt hardware priority is given in this order from the
and
TRAP
Figure 20
Doc ID 17660 Rev 1
IT1
IT0
Table 20: Interrupt
show two different interrupt management modes. The
IT3
IT4
mapping). When several pending
10
SOFTWARE
PRIORITY
LEVEL
MAIN
3
3
3
3
3
3
3/0
I1
1 1
1 1
1 1
1 1
1 1
1 1
Interrupts
I0
55/276