ST7MC2R6 STMicroelectronics, ST7MC2R6 Datasheet - Page 278

• Manufacturer Part Number: ST7MC2R6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2R6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
12.12.3 Input Stage (Current Feedback Comparator + Sampling)
Notes:
1. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of
the comparator and must be avoided:
– Negative injection current on the I/Os close to the comparator inputs
– Switching on I/Os close to the comparator inputs
– Negative injection current on not used comparator input (MCCFI0 or MCCFI1)
– Switching with a high dV/dt on not used comparator input (MCCFI0 or MCCFI1)
These phenomena are even more critical when a big external serial resistor is added on the inputs.
2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.
3.This delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput chang-
es.
Example: When CFF=0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle
after comparator commutation, i.e. there is a variation of (1/f
278/309
Symbol
t
sampling
t
t
V
I
propag
startup
offset
V
offset
IN
Comparator input voltage range
Comparator offset error
Input offset current
Comparator propagation
delay
Start-up filter duration
Digital sampling delay
1)
Parameter
2)
3)
Time waited before sampling
when comparator is turned
ON, i.e. CKE=1 or DAC=1
(with f
Time needed to turn OFF the
MCOs when comparator out-
put rises (CFF=0)
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF=0)
Time needed to turn OFF the
MCOs when comparator out-
put rises (CFF=x)
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF=x)
PERIPH
Conditions
= 4MHz)
mtc
) or (4 / f
PERIPH
V
SSA
) depending on the case.
Min
- 0.1
(1+x) * (4 / f
(1+x) * (4 / f
4 / f
2 / f
MTC
MTC
(see
(see
Typ
35
5
3
(see
(see
Figure
Figure
PERIPH
PERIPH
Figure
Figure
) + (3 / f
) + (1 / f
V
156)
156)
DD
Max
40
100
155)
+ 0.1
1
155)
1)
mtc
mtc
)
)
Unit
mV
μA
ns
μs
V