ST7MC2R6 STMicroelectronics, ST7MC2R6 Datasheet - Page 91

• Manufacturer Part Number: ST7MC2R6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2R6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 =
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
Bit 6 =
0: No match (reset value).
1: The content of the free running counter has
Bit 5 =
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
ICF1 OCF1
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
7
(Cont’d)
TOF
ICF2 OCF2 TIMD
0
0
0
not clear TOF.
Bit 4 =
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
Bit 3 =
0: No match (reset value).
1: The content of the free running counter has
Bit 2 =
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Reading or writing the ACLR register does
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