ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 27

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
t
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
t
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
(see
Figure 14. RESET Sequences
w(RSTL)out
w(RSTL)out
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
“OPERATING CONDITIONS” on page
V
V
IT+(LVD)
IT-(LVD)
Figure
.
(see short ext. Reset in
RUN
V
14). Starting from the external RE-
DD
ACTIVE PHASE
DD
RESET
LVD
is over the minimum
OSC
Figure
t
t
frequency.
w(RSTL)out
h(RSTL)in
RUN
14), the
140)
ACTIVE
PHASE
SHORT EXT.
RESET
DELAY
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
t
Power-On RESET
Voltage Drop RESET
h(RSTL)in
t
w(RSTL)out
<V
RUN
ST72321Rx ST72321ARx ST72321Jx
IT-
(falling edge) as shown in
WATCHDOG UNDERFLOW
ACTIVE
PHASE
LONG EXT.
RESET
w(RSTL)out
DD
<V
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
RUN
DD
IT+
.
larger than t
ACTIVE
(rising edge) or
PHASE
WATCHDOG
RESET
t
w(RSTL)out
Figure
Figure
DD
g(VDD)
14.
supply
RUN
27/193
CPU
14.
to
)