ST72321AR7 STMicroelectronics, ST72321AR7 Datasheet - Page 37

• Manufacturer Part Number: ST72321AR7
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR7

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
3. Only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■
■
■
N°
10
11
12
13
Falling edge
Rising edge
Falling and rising edge
0
1
2
3
4
5
6
7
8
9
22). This control allows to have up to 4 fully
MCC/RTC
PWM ART
TIMER A
TIMER B
Source
RESET
Block
TRAP
AVD
SCI
SPI
I2C
TLI
ei0
ei1
ei2
ei3
Reset
Software interrupt
External top level interrupt
Main clock controller time base interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
I2C Peripheral interrupts
PWM ART interrupt
Not used
Description
■
■
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
ST72321Rx ST72321ARx ST72321Jx
(see periph)
ARTCSR
Register
SPICSR
MCCSR
SCISR
SICSR
Label
TASR
TBSR
EICR
N/A
N/A
Priority
Priority
Priority
Higher
Order
Lower
HALT
from
yes
yes
Exit
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
1
2
3)
FFECh-FFEDh
FFFCh-FFFDh
FFEAh-FFEBh
FFFAh-FFFBh
FFEEh-FFEFh
FFFEh-FFFFh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Address
Vector
37/193