ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 187

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ST72361J6

Manufacturer Part Number
ST72361J6
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72361J6

Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 PLL Characteristics
Notes:
1. Data characterized but not tested.
2. Under characterization
Figure 101. PLL Jitter vs Signal Frequency
Notes:
1. Measurement conditions: f
Operating conditions: V
V
f
Δ f
OSC
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Voltage Range
PLL input frequency range
PLL jitter
Application Signal Frequency (KHz)
1000
Parameter
1)
DD
CPU
500
3.8 to 5.5V @ T
= 4 MHz, T
250
PLL ON
PLL OFF
A
T
T
f
f
OSC
OSC
= 25°C
A
A
125
= 0 to +70
= -40 to +125
A
= 4 MHz, V
= 2 MHz, V
0 to 70°C
1)
Conditions
°
C
DD
DD
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore, the longer the
period of the application signal, the less it is im-
pacted by the PLL jitter.
Figure 101
plication signals in the range 125 kHz to 2 MHz. At
frequencies of less than 125 kHz, the jitter is neg-
ligible.
1)
°
C
or V
= 4.5 to 5.5V
= 4.5 to 5.5V
DD
4.5 to 5.5V @ T
shows the PLL jitter integrated on ap-
Min
3.8
4.5
2
A
Typ
-40 to 125°C
Note 2
Max
5.5
4
ST72361
187/225
MHz
Unit
%

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