ST72361AR9-Auto STMicroelectronics, ST72361AR9-Auto Datasheet - Page 133

• Manufacturer Part Number: ST72361AR9-Auto
• Description: 8-bit MCU for automotive with K Flash, 10-bit ADC, 5 Timers, SPI, 2x LINSCI
• Manufacturer: STMicroelectronics

Specifications of ST72361AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72361xx-Auto
Note:
1
2
3
4
5
Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t
f
PRESC
Table
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
CPU
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
55)
=
=
=
Pulse period (in seconds)
PLL output x2 clock frequency in hertz (or f
Timer prescaler factor (2, 4, 8 or 8000 depending on the CC[1:0] bits, see
event occurs
on ICAP1
Doc ID 12468 Rev 3
Counter
= OC1R
When
When
OCiR Value =
One pulse mode cycle
OCMP1 = OLVL2
Figure
OCMP1 = OLVL1
Counter is reset
ICR1 = Counter
ICF1 bit is set
PRESC
t
to FCh
*
f
CPU
68).
- 5
OSC
/2 if PLL is not enabled)
8-bit timer (TIM8)
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