ST72321AR6 STMicroelectronics, ST72321AR6 Datasheet - Page 24

• Manufacturer Part Number: ST72321AR6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321Rx ST72321ARx ST72321Jx
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
■
■
■
■
Figure 11. Clock, Reset and Supply Block Diagram
24/193
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
RESET
OSC2
OSC1
capability for monitoring the main supply or
the EVD pin
V
V
EVD
SS
DD
Figure
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
11.
f
OSC
(option)
PLL
SICSR
AVD AVD AVD LVD
SYSTEM INTEGRITY MANAGEMENT
S
0
1
IE
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 151.
Figure 10. PLL Block Diagram
f
OSC
AVD Interrupt Request
AUXILIARY VOLTAGE
F
LOW VOLTAGE
RF
DETECTOR
DETECTOR
(AVD)
(LVD)
0
PLL x 2
0
/ 2
OSC2 =
0
WDG
f
RF
OSC2
f
OSC
PLL OPTION BIT
/2.
CLOCK (MCC/RTC)
WITH REALTIME
0
1
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
OSC2
f
OSC2
of 4 to 8
f
CPU