LNBP21 STMicroelectronics, LNBP21 Datasheet - Page 2

• Manufacturer Part Number: LNBP21
• Description: LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
• Manufacturer: STMicroelectronics

LNBP21
power dissipation together with simple design and
I
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit will
disable the whole circuit when the supplied V
drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I
dedicated pin (DSQIN) that allows immediate
DiSEqC
this IC are controlled via I
bits on the System Register (SR, 8 bits). The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pins is closed, thus leaving all LNB
powering and control functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible to
increment by 1V (typ.) the selected voltage value
to compensate for the excess voltage drop along
the coaxial cable (LLC bit HIGH). In order to
minimize the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless of
the DSQIN pin logic status. The TEN bit must be
set LOW when the DSQIN pin is used for
DiSEqC
DiSEqC
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC
extracted PWK data are available on the
DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking
capacitor must be used to couple the modulating
signal source to the EXTM pin. When external
(*): External components are needed to comply to bi-directional DiSEqC
cation to DiSEqC
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be
externally limited.
2/24
2
C
TM
standard interfacing.
TM
TM
TM
interfacing is completed by the built-in
data encoding (*). All the functions of
TM
encoding. The
specifications is not implied by the use of this IC.
2
C
2
C
TM
TM
fully
interface or by a
TM
bus by writing 6
bus, and the
bidirectional
CC
TM
modulation is not used, the relevant pin can be left
open.
The current limitation block has two thresholds
that can be selected by the I
lower threshold is between 400 and 550mA
(I
between 500 and 650mA (I
The current protection block is SOA type. This
limits the short circuit current (I
200mA with I
I
ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dynamically by the PCL bit of the SR; when the
PCL (Pulsed Current Limiting) bit is set to LOW,
the
dynamically: as soon as an overload is detected,
the output is shut-down for a time t
900ms. Simultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
10t
detected, the protection circuit will cycle again
through T
which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
T
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**).
However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in static mode (PCL=HIGH) and then
switching to the dynamic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
This IC is also protected against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140°C (typ.).
SEL
SEL
on
bus hardware requirements. Full compliance of the whole appli-
off
+T
=LOW when the output port is connected to
=HIGH), while the higher threshold is
(typ.). At the end of t
off
overcurrent
time is 990ms and it is determined by an
off
and T
SEL
on
=HIGH and at 300mA with
.
protection
At the end of a full Ton in
on
SEL
, if the overload is still
SEL
=LOW).
bit of the SR; the
SC
circuit
) typically at
off
, typically
works
on
=1/