LNBP21 STMicroelectronics, LNBP21 Datasheet - Page 5

• Manufacturer Part Number: LNBP21
• Description: LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
• Manufacturer: STMicroelectronics

Figure 3: Typical Application Circuit
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT recommendation to implement the DiSEqC
not implemented (see DiSEqC implementation note)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel MosFet (STN4NF03L or similar)
I
Data transmission from main µP to the LNBP21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig. 4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
2
C BUS INTERFACE
(Note 3)
(Note 3)
IC2
IC2
L1=22µH
L1=22µH
12V
12V
Vin
Vin
STS4DNFS30L
STS4DNFS30L
STS4DNFS30L
STS4DNFS30L
R
R
R
R
0.1
0.1
0.1
0.1
sc
sc
sc
sc
C1
C1
C1
C1
220µF
220µF
220µF
220µF
C2
C2
220µF
220µF
(Note 4)
(Note 4)
C4
C4
C4
C4
470nF
470nF
470nF
470nF
Ceramic
Ceramic
Ceramic
Ceramic
C3
C3
C3
C3
470nF
470nF
470nF
470nF
Ceramic
Ceramic
Ceramic
Ceramic
IC1
IC1
Vup
Vup
Gate
Gate
Sense
Sense
Vcc
Vcc
DSQIN(Note 1)
DSQIN(Note 1)
SCL
SCL
SDA
SDA
LNBP21
LNBP21
D1 1N4001
D1 1N4001
D1 1N4001
D1 1N4001
GND
GND
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig.
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBP21 won't generate the acknowledge if
the V
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBP21, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
ADDRESS
ADDRESS
CC
DSQOUT
DSQOUT
DETIN
DETIN
(Note 1)
(Note 1)
4).
EXTM
EXTM
Byp
Byp
supply is below the Undervoltage Lockout
LT1
LT1
LT2
LT2
Vo
Vo
TM
The
C8
C8
10nF
10nF
2.x, not needed if bidirectional DiSEqC
C5
C5
470nF
470nF
peripheral
C6
C6
10nF
10nF
D2
D2
D2
D2
BAT43
BAT43
BAT43
BAT43
C7
C7
C7
C7
10nF
10nF
10nF
10nF
0<Vaddr<V
0<Vaddr<V
Master STB
Master STB
see Note 2
see Note 2
15 ohm
15 ohm
270µH
270µH
B yp
B yp
(LNBP21)
to LNB
to LNB
LNBP21
TM
2.x is
5/24
that