MAXQ613 Maxim, MAXQ613 Datasheet - Page 13

• Manufacturer Part Number: MAXQ613
• Description: The MAXQ613 is a low-power, 16-bit MAXQ® microcontroller designed for low-power applications including universal remote controls, consumer electronics, and white goods
• Manufacturer: Maxim

Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
different password locks are provided, each of which
can be used to protect a different area of memory (sys-
tem memory, user loader, and user application). Each
password lock is controlled by a 16-word area of flash
memory; if the password is set to all FFFFh values or all
0000h values, the password is disabled. Otherwise, the
password is active and must be matched by the user of
the bootloader or debugger before access is granted to
the corresponding area of flash program memory. Refer
to the MAXQ610 User’s Guide for more details.
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the applica-
tion software. If software is operating correctly, the coun-
ter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
2
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires. See Table 2.
15
WD[1:0]
to 2
00
01
10
11
24
16-Bit Microcontroller with Infrared Module
system clock cycles. An interrupt is gener-
WATCHDOG CLOCK
______________________________________________________________________________________
Sysclk/2
Sysclk/2
Sysclk/2
Sysclk/2
Watchdog Timer
15
18
21
24
WATCHDOG INTERRUPT TIMEOUT
174.7ms
21.9ms
2.7ms
1.4s
The dedicated IR timer/counter module simplifies low-
speed infrared (IR) communication. The IR timer imple-
ments two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of a carrier generator and a
carrier modulator. The carrier generation module uses
the 16-bit IR carrier register (IRCA) to define the high
and low time of the carrier through the IR carrier high
byte (IRCAH) and IR carrier low byte (IRCAL). The carrier
modulator uses the IR data bit (IRDATA) and IR modula-
tor time register (IRMT) to determine whether the carrier
or the idle condition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the begin-
ning value for the carrier modulator. During transmission,
the IRV register is initially loaded with the IRMT value
and begins down counting towards 0000h, whereas
in receive mode it counts upward from the initial IRV
register value. During the receive operation, the IRV
register can be configured to reload with 0000h when
capture occurs on detection of selected edges or can be
allowed to continue free-running throughout the receive
operation. An overflow occurs when the IR timer value
rolls over from 0FFFFh to 0000h. The IR overflow flag
(IROV) is set to 1 and an interrupt is generated if enabled
(IRIE = 1).
and Modulation Timer
IR Carrier Generation
WATCHDOG INTERRUPT (µs)
WATCHDOG RESET AFTER
42.7
42.7
42.7
42.7
13