MAX9242 Maxim, MAX9242 Datasheet - Page 5

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MAX9242

Manufacturer Part Number
MAX9242
Description
The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs
Manufacturer
Maxim
Datasheet

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Part Number
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Quantity
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Part Number:
MAX9242EUM+T
Manufacturer:
MAXIM
Quantity:
3
AC ELECTRICAL CHARACTERISTICS (continued)
(V
DCB = high or low, differential input voltage |V
otherwise noted. Typical values are at V
Spread-Spectrum Modulation
Frequency
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
Note 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
Note 4: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Note 5: One output shorted at a time. Current out of the pin.
Note 6: V
Note 7: C
Note 8: RCIP is the period of RxCLKIN_. RCOP is the period of RxCLKOUT.
Note 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN_.
RxCLKOUT High Time
RxCLKOUT Low Time
RxOUT_ Setup to RxCLKOUT
RxOUT_ Hold from RxCLKOUT
RxCLKIN_ to RxCLKOUT Delay
Deserializer Phase-Locked-
Loop Set
Deserializer Power-Down Delay
Deserializer Phase-Locked-
Loop Set from SSG Change
Spread-Spectrum Output
Frequency
CC
= LVDSV
except V
tested at T
must be less than ±10µA.
at ±6 sigma.
PARAMETER
TH
L
includes probe and test jig capacitance.
, V
CC
TL
, and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
TH
= PLLV
A
_______________________________________________________________________________________
and V
= +25°C.
21-Bit Deserializers with Programmable
CC
TL
.
= +3.0V to +3.6V, V
f
SYMBOL
RxCLKOUT
RPLLS2
RCOH
RPLLS
RHRC
RCCD
RCOL
RSRC
RPDD
CC
f
SSM
Spread Spectrum and DC Balance
= V
CCO
ID
Figures 5a, 5b
Figures 5a, 5b
Figures 5a, 5b
Figures 5a, 5b
SSG = low, Figures 6a, 6b
Figure 7
Figure 8
Figure 9
| = 0.1V to 1.2V, input common-mode voltage V
SSG = high,
Figure 10
SSG = open,
Figure 10
SSG = low
Figure 10
= LVDSV
CCO
= +3.0V to +3.6V, C
CC
= PLLV
CONDITIONS
CC
= +3.3V, |V
M axi m um outp ut
fr eq uency
Minimum output
frequency
M axi m um outp ut
fr eq uency
Minimum output
frequency
L
= 8pF, PWRDWN = high; SSG = high, open, or low;
ID
| = 0.2V, V
(RCIP / 2)
f
f
f
f
f
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
+ 3.6%
+ 1.8%
- 4.4%
- 2.2%
CM
0.35 x
RCOP
0.35 x
RCOP
RCOP
0.45 x
RCOP
4.5 +
0.3 x
MIN
CM
= +1.25V, T
= |V
f
ID
(RCIP / 2)
f
f
f
f
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
+ 4.0%
+ 2.0%
- 4.0%
- 2.0%
/ 2| to 2.4V - |V
6.5 +
1016
TYP
A
= +25°C.) (Notes 6, 7, 8)
/
(RCIP / 2)
f
f
f
f
f
65,600 x
32,800 x
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
RxCLKIN_
+ 4.4%
+ 2.2%
- 3.6%
- 1.8%
MAX
8.2 +
RCIP
RCIP
100
ID
/ 2|, unless
UNITS
MHz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
5

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