TMP86xy09NG Toshiba, TMP86xy09NG Datasheet - Page 71

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TMP86xy09NG

Manufacturer Part Number
TMP86xy09NG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy09NG

Package
SDIP32
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
8/16
Ram Size
256/512
Driver Led
8
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
-
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
6
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Dual Clock
Clock Gear
-
Number Of I/o Ports
26
Power Supply (v)
2.7 to 5.5
7.2.5 Watchdog Timer Reset
Clock
Binary counter
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
1
Figure 7-2 Watchdog Timer Interrupt
Write 4E
2
H
to WDTCR2
3
2
17
/fc
0
Page 61
1
2
19
/fc [s]
2
3
A reset occurs
0
TMP86C809NG
(WDTT=11)

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