IR3550MTRPBF International Rectifier, IR3550MTRPBF Datasheet - Page 14

• Manufacturer Part Number: IR3550MTRPBF
• Description: The IR3550 integrated PowIRstage is a synchronous buck gate driver IC with co-packed control and synchronous MOSFETs and Schottky diode.
• Manufacturer: International Rectifier

Specifications of IR3550MTRPBF

• Package: PQFN / 6 x 6
• Iout (a): 60
• Switch Freq (khz): up to 1.0MHz
• Input Range (v): 4.5 - 15
• Output Range (v): 0.25 - (VCC -2.5)

is de-biased and turn off the synchronous MOSFET,
allowing the switch node to float.
This is in contrast to the Body-Braking® mode shown in
Figure 23, where GATEL follows PWM input. The Schottky
diode in parallel with the synchronous MOSFET conducts
for a longer period of time and therefore lowers the light
load efficiency.
The zero current detection circuit in the IR3550 is
independent of the current sense amplifier and therefore
still functions even if the current sense amplifier is not
used. As shown in Figure 6, an offset is added to the diode
emulation comparator so that a slightly positive output
current in the inductor and synchronous MOSFET is treated
as zero current to accommodate propagation delays,
preventing
synchronous MOSFET. This causes the Schottky diode in
parallel with the synchronous MOSFET to conduct before
the inductor current actually reaches zero, and the
conduction time increases with inductance of the output
inductor.
To set the IR3550 in diode emulation mode, the BBRK# pin
must be toggled low at least once after the VCC passes its
UVLO threshold during power up. One simple way is to use
the internal BBRK# pull-up resistor (200kΩ typical) with an
external capacitor from BBRK# pin to LGND, as shown in
Figure 4. To ensure the diode emulation mode is properly
set, the BBRK# voltage should be lower than 0.8V when the
VCC voltage passes its UVLO threshold (3.3V minimum and
3.7V typical), as shown in Figure 24. A digital signal from
the PWM controller can also be used to set the diode
emulation mode. The BBRK# signal can either be pulled
low for at least 20ns after the VCC passes its UVLO
threshold, as shown in Figure 25, or be pulled low before
VCC power up and then released after the VCC passes its
UVLO threshold, as shown in Figure 26.
Once the diode emulation mode is set, it cannot be reset
until the VCC power is recycled.
PHASE FAULT AND THERMAL FLAG OUTPUT
The phase fault circuit looks at the switch node with
respect to ground to determine whether there is a
defective MOSFET in the phase. The output of the phase
fault signal is high during normal operation and is pulled
low when there is a fault. Each driver monitors the
MOSFET it drives. If the switch node is less than a certain
voltage above ground when the PWM signal goes low or
if the switch node is a certain voltage above ground when
the PWM signal rises, this gives a fault signal. If there are a
14
any
March 12, 2012 | FINAL DATASHEET
negative
current
flowing
in
60A Integrated PowIRstage®
the
number of consecutive faults the phase fault signal is
asserted.
Thermal flag circuit monitors the temperature of the
IR3550. If the temperature goes above a threshold (160°C
typical) the PHSFLT# pin is pulled low after a maximum
delay of 100us.
The PHSFLT# pin can be pulled low by either the phase
fault circuit or the thermal flag circuit. The phase fault
signal could be used to turn off the AC/DC converter or
blow a fuse to disconnect the DC/DC converter input from
the supply.
If PHSFLT# is not used it can be floated or connected to
LGND.
LOSSLESS AVERAGE INDUCTOR CURRENT
SENSING
Inductor current can be sensed by connecting a series
resistor and a capacitor network in parallel with the
inductor and measuring the voltage across the capacitor,
as shown in Figure 31.
The equation of the current sensing network is as follows.
Usually the resistor R
the time constant of R
v
CS
(
s
Amplifier
IR3550
Current
)
Sense


v
i
L
L
(
(
Figure 31: Inductor current sensing
+
s
-
s
)
)
1
R
CSIN+
CSIN-

L
VIN
SW
sR
CS
when
1
and capacitor C
CS
CS
i
L
C
and C
CS
L
+
R
R

CS
CS
L
L
CIN
i
L
equals the inductor time

v
(
V
L
C
s
R
IN
+ v
CS
)
CS
R
CS
R
CS
-
L
C
L
are chosen so that
IR3550
-
CS
1

1

sR
s
CS
R
L
C
COUT
V
L
OUT
CS