FAN6920MR Fairchild Semiconductor, FAN6920MR Datasheet - Page 17

• Manufacturer Part Number: FAN6920MR
• Description: The highly integrated FAN6920MR combines Power Factor Correction (PFC) controller and quasi-resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.5
RANGE Pin
A built-in low-voltage MOSFET can be turned on or off
according to V
drain pin of this internal MOSFET is connected to the
RANGE pin. Figure 29 shows the status curve of V
voltage level and RANGE impedance (open or ground).
Zero-Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when PFC MOS is
off, the stored energy of the PFC inductor starts to
release to the output load. Then the drain voltage of
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin
voltage is lower than the triggering voltage (1.75V
typical), the PFC gate signal is sent again to start a new
switching cycle.
If PFC operation needs to be shut down due to
abnormal condition, pull the ZCD pin LOW, voltage
under 0.2V (typical), to activate the PFC disable function
to stop PFC switching operation.
For preventing excessive high switching frequency at
light load, a built-in inhibit timer is used to limit the
minimum t
detected, the PFC gate signal is not sent during the
inhibit time (2.5µs typical).
Figure 29. Hysteresis Behavior between RANGE Pin
Figure 30. Internal Block of the Zero-Current
OFF
time. Even if the ZCD signal has been
VIN
voltage level and PFC status. The
and VIN Pin Voltage
Detection
VIN
Protection for PFC Stage
PFC Output Voltage UVP and OVP (INV Pin)
FAN6920MR provides several kinds of protection for
PFC stage. PFC output over- and under-voltage are
essential for PFC stage. Both are detected and
determined by INV pin voltage, as shown in Figure 32.
When INV pin voltage is over 2.75V or under 0.45V, due
to overshoot or abnormal conditions, and lasts for a de-
bounce time around 70µs; the OVP or UVP circuit is
activated to stop PFC switching operation immediately.
The INV pin is not only used to receive and regulate
PFC output voltage; it can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
17
PFCVO
V
Gate
PFC
IN,MAX
1.75V
V
Figure 31. Operation Waveforms of PFC
2.1V
10V
V
ZCD
Figure 32. Internal Block of PFC Over-
DS
Zero-Current Detection
and Under-Voltage Protection
Inhibit
Time
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t
t
t