FAN6920MR Fairchild Semiconductor, FAN6920MR Datasheet - Page 3

• Manufacturer Part Number: FAN6920MR
• Description: The highly integrated FAN6920MR combines Power Factor Correction (PFC) controller and quasi-resonant PWM controller
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.5
Internal Block Diagram
CSPWM
CSPFC
INV
DET
FB
10
11
5
3
4
2.65V
2.75V
Blanking
(2.5µs)
RANGE
2.3V
t
OFF
GND
5V
Blanking
Soft-Start
Compensation
9
Circuit
Over-Power
(5µs/20.5µs/2.25ms)
2.5V
5ms
Multi-Vector Amp.
I
Blanking
DET
Circuit
t
OFF-MIN
5V
S/H
Internal
OTP
COMP
0.82V
V
2.5V
4.2V
I
DET
0.7V
2
2R
DET
V
Current Limit
R
COMP-H
2.75V
2.9V
DET OVP
PWM
I
DET
Auto-Recovery
V
I
COMP-BURST
CTRL-PFC
COMP-H
RANGE
Figure 2. Functional Block Diagram
0.45V
Current Limit
Optimizer
PFC
100µA
THD
Auto-Recovery
Detector
V
(30µA)
Valley
COMP-L
I
RT
OVP
UVP
COMP-L
2.25ms
28µs
12
RT
HV
16
0.8V
0.5V
Valley
I
HV
Starter
Timer
1st
Debounce
50ms
/ Externally Triggering
Debounce
70µs
27.5V
Prog. OTP
VB
Auto-Recovery
t
OFF-MIN
+9µs
Debounce
COMP-L
Time
3
OVP
Auto-Recovery
PFC Burst Mode
Brownout
COMP-H
Generator
Sawtooth
FB OLP
100µs
10ms
t
on-max
Recovery
V
Auto-
COMP-H
Auto-Recovery
1V/1.2V
12V/7V/5V
Protection
Two-Step
2.3V/0.8V
Brownout
VDD
UVLO
1.2V
V
VIN
13
7
Auto-Recovery
INV
Function
V
Disable
INV
V
V
INV
IN
2.4V/2.25V
Comparator
(RT Pin) Externally Triggering
0.2V
Brownout
PWM-ON/OFF
0.7V
S
R
Restarter
Inhibit
Timer
(RT Pin) Prog. OTP
PFC RANGE Control
Startup
SET
CLR
Q
Q
S
R
VDD Pin OVP
DET Pin OVP
Internal OTP
SET
CLR
Debounce
Debounce
100mS
Q
Q
V
V
comp
B
I
ZCD
& Clamp
to 1.6V
PFC Zero-Current
PFC Burst Mode
Internal
Bias
DRV
DRV
Detector
Protection
17.5V
Recovery
2.1V/1.75V
Auto-
10V
15.5V
15
14
6
8
1
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RANGE
ZCD
OPFC
NC
OPWM